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Initial. Don't... just don't ask.

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Ryan McGrath 2011-02-24 00:22:00 -08:00
commit 00bae13bba
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1
obsolete/et4000/0-README Normal file
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Please read 'man 7 svgalib.et4000'

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/*
This is for a Cardex ET4000/W32, with a high-end monitor (it uses
58 kHz horizontal sync for 1024x768 non-int at 70 Hz).
--HH
*/
/*
( File generated by tseng3.exe )
tseng3 v1.2, Copyright (C) 1993 Tommy Frandsen, Harm Hanemaayer
and Hartmut Schirmer
Permission is granted to any individual or institution to use, copy, or
redistribute this executable so long as it is not modified and that it is
not sold for profit.
LIKE ANYTHING ELSE THAT'S FREE, TSENG3 IS PROVIDED AS IS AND COMES WITH
NO WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED. IN NO EVENT WILL
THE COPYRIGHT HOLDERS BE LIABLE FOR ANY DAMAGES RESULTING FROM THE USE OF
THIS SOFTWARE.
*/
/* Music 15/16/24 bit dac (AT&T compatible) detected */
#define DAC_TYPE 9
#define CLOCK_VALUES { \
/* 0 */ 50350, \
/* 1 */ 56644, \
/* 2 */ 65293, \
/* 3 */ 72364, \
/* 4 */ 80429, \
/* 5 */ 90155, \
/* 6 */ 63300, \
/* 7 */ 75379 \
}
/* VESA HiColor mode 0x10D -- 320x200x32K */
/* Video timing: Vertical frequency : 69.8Hz
Horizontal frequency : 31.3KHz */
static unsigned char g320x200x32K_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0xBF,0x1F,0x00,0x41,0x00,0x00,
0x00,0x00,0x00,0x00,0x9C,0x8E,0x8F,0x50,0x60,0x96,0xB9,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x63,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xFC,0x00,0x00,
0x80
};
/* VESA HiColor mode 0x10E -- 320x200x64K */
#define g320x200x64K_regs g320x200x32K_regs
/* ET4000 TrueColor BIOS mode 0x13 -- 320x200x16M : NOT SUPPORTED */
#define g320x200x16M_regs DISABLE_MODE
/* VESA mode 0x101 -- 640x480x256 */
/* Video timing: Vertical frequency : 59.7Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x480x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0xEA,0x8C,0xDF,0x50,0x60,0xE7,0x04,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xE3,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xFC,0x00,0x00,
0x00
};
/* VESA HiColor mode 0x110 -- 640x480x32K */
/* Video timing: Vertical frequency : 59.7Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x480x32K_regs[73] = {
0xC3,0x9F,0xA1,0x85,0xA7,0x1F,0x0B,0x3E,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0xEA,0x8C,0xDF,0xA0,0x60,0xE7,0x04,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xE3,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x80
};
/* VESA HiColor mode 0x111 -- 640x480x64K */
#define g640x480x64K_regs g640x480x32K_regs
/* VESA TrueColor mode 0x112 -- 640x480x16M */
/* Video timing: Vertical frequency : 59.6Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x480x16M_regs[73] = {
0x27,0xEF,0xF2,0x88,0xF8,0x98,0x0B,0x3E,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0xEA,0x0C,0xDF,0xF0,0x60,0xE7,0x04,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xEF,
0x1C,0x00,0x28,0x00,0x0A,0x00,0x2B,0x0F,0x01,0xBC,0x00,0x00,
0x80
};
/* VESA mode 0x102 -- 800x600x16 */
/* Video timing: Vertical frequency : 72.4Hz
Horizontal frequency : 48.2KHz */
static unsigned char g800x600x16_regs[73] = {
0x7D,0x63,0x63,0x81,0x6D,0x1C,0x98,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x7C,0x82,0x57,0x32,0x00,0x57,0x99,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x0F,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x06,
0x23,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x00
};
/* VESA mode 0x103 -- 800x600x256 */
/* Video timing: Vertical frequency : 72.4Hz
Horizontal frequency : 48.2KHz */
static unsigned char g800x600x256_regs[73] = {
0x7D,0x63,0x64,0x80,0x6D,0x1C,0x98,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x7C,0x82,0x57,0x64,0x60,0x5D,0x93,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x23,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x00
};
/* VESA HiColor mode 0x113 -- 800x600x32K */
/* Video timing: Vertical frequency : 60.8Hz
Horizontal frequency : 38.5KHz */
static unsigned char g800x600x32K_regs[73] = {
0xFF,0xC7,0xC9,0x81,0xD1,0x11,0x77,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x5D,0x8F,0x57,0xC8,0x60,0x5B,0x74,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xE3,
0x1C,0x00,0x28,0x00,0x0A,0x00,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x80
};
/* VESA HiColor mode 0x114 -- 800x600x64K */
#define g800x600x64K_regs g800x600x32K_regs
/* ET4000 TrueColor BIOS mode 0x30 -- 800x600x16M : NOT SUPPORTED */
/* VESA mode 0x104 -- 1024x768x16 */
/* Video timing: Vertical frequency : 71.8Hz
Horizontal frequency : 57.8KHz */
static unsigned char g1024x768x16_regs[73] = {
0xA8,0x7F,0x7F,0x8C,0x87,0x98,0x24,0xF5,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x02,0x88,0xFF,0x40,0x00,0xFF,0x25,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x0F,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x06,
0xE3,
0x1C,0x00,0x28,0x00,0x0A,0x00,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x00
};
/* VESA mode 0x105 -- 1024x768x256 */
/* Video timing: Vertical frequency : 71.8Hz
Horizontal frequency : 57.8KHz */
static unsigned char g1024x768x256_regs[73] = {
0xA8,0x7F,0x7F,0x8C,0x87,0x98,0x24,0xF5,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x02,0x88,0xFF,0x80,0x60,0xFF,0x25,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xE3,
0x1C,0x00,0x28,0x00,0x0A,0x00,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x38 -- 1024x768x32K : NOT SUPPORTED */
/* ET4000 HiColor BIOS mode 0x38 -- 1024x768x64K : NOT SUPPORTED */
/* ET4000 TrueColor BIOS mode 0x38 -- 1024x768x16M : NOT SUPPORTED */
/* VESA mode 0x106 -- 1280x1024x16 */
/* Video timing: Vertical frequency : 43.5Hz (interlaced)
Horizontal frequency : 48.1KHz */
static unsigned char g1280x1024x16_regs[73] = {
0xCB,0x9F,0xA0,0x8E,0xA9,0x04,0x4F,0x52,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x11,0x89,0xFF,0x50,0x00,0x09,0x46,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x0F,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x06,
0x23,
0x1C,0x00,0x28,0x00,0x0A,0x9B,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x00
};
/* VESA mode 0x107 -- 1280x1024x256 : NOT SUPPORTED */
/* VESA HiColor mode 0x119 -- 1280x1024x32K : NOT SUPPORTED */
/* VESA HiColor mode 0x11A -- 1280x1024x64K : NOT SUPPORTED */
/* VESA TrueColor mode 0x11B -- 1280x1024x16M : NOT SUPPORTED */
/* --- ET4000 specific modes */
#ifdef _DYNAMIC_ONLY_
/* ET4000 BIOS mode 0x2D -- 640x350x256 */
/* Video timing: Vertical frequency : 69.8Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x350x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x83,0x85,0x5D,0x50,0x60,0x63,0xBA,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xA3,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xFC,0x00,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x2D -- 640x350x32K */
/* Video timing: Vertical frequency : 69.8Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x350x32K_regs[73] = {
0xC3,0x9F,0xA1,0x85,0xA7,0x1F,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x83,0x85,0x5D,0xA0,0x60,0x63,0xBA,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xA3,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x80
};
/* ET4000 HiColor BIOS mode 0x2D -- 640x350x64K */
#define g640x350x64K_regs g640x350x32K_regs
/* ET4000 TrueColor BIOS mode 0x2D -- 640x350x16M */
/* Video timing: Vertical frequency : 69.6Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x350x16M_regs[73] = {
0x27,0xEF,0xF2,0x88,0xF8,0x98,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x83,0x05,0x5D,0xF0,0x60,0x63,0xBA,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xAF,
0x1C,0x00,0x28,0x00,0x0A,0x00,0x2B,0x0F,0x01,0xBC,0x00,0x00,
0x80
};
/* VESA mode 0x100 -- 640x400x256 */
/* Video timing: Vertical frequency : 69.8Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x400x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x9C,0x8E,0x8F,0x50,0x60,0x96,0xB9,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x63,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xFC,0x00,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x2F -- 640x400x32K */
/* Video timing: Vertical frequency : 69.8Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x400x32K_regs[73] = {
0xC3,0x9F,0xA1,0x85,0xA7,0x1F,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x9C,0x8E,0x8F,0xA0,0x60,0x96,0xB9,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x63,
0x1C,0x00,0x28,0x00,0x08,0x00,0x2B,0x0F,0x00,0xBC,0x00,0x00,
0x80
};
/* ET4000 HiColor BIOS mode 0x2F -- 640x400x64K */
#define g640x400x64K_regs g640x400x32K_regs
/* ET4000 TrueColor BIOS mode 0x2F -- 640x400x16M */
/* Video timing: Vertical frequency : 69.6Hz
Horizontal frequency : 31.3KHz */
static unsigned char g640x400x16M_regs[73] = {
0x27,0xEF,0xF2,0x88,0xF8,0x98,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x9C,0x0E,0x8F,0xF0,0x60,0x96,0xB9,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x6F,
0x1C,0x00,0x28,0x00,0x0A,0x00,0x2B,0x0F,0x01,0xBC,0x00,0x00,
0x80
};
#endif /* defined(_DYNAMIC_ONLY_ALL_) */

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/* ET4000 registers from SVGALIB 0.81 */
/* Define DAC_TYPE to force the DAC type used in the ET4000 driver. If it */
/* is not defined, the driver tries to autodetect the DAC type which may go */
/* wrong. */
/* Use the following values:
0: Ordinary DAC
1: Sierra SC11486 (32k)
3: Sierra 32k/64k
5: SS2410 15/24bit DAC
9: AT&T 20c491/2 (32k/64k/24bit)
17: Acumos ADAC (Cirrus Logic DAC)
33: Sierra 15025/6 24-bit DAC
*/
#define DAC_TYPE 0
/* unsupported modes */
#define g320x200x64K_regs DISABLE_MODE
#define g320x200x16M_regs DISABLE_MODE
#define g800x600x16_regs DISABLE_MODE
#define g1024x768x16_regs DISABLE_MODE
#define g1280x1024x16_regs DISABLE_MODE
/* Got this mode from someone's tseng3.exe dump. */
/* ET4000 HiColor BIOS mode 0x13 -- 320x200x32K */
/* Video timing: Vertical frequency : 70.3Hz
Horizontal frequency : 31.6KHz */
static unsigned char g320x200x32K_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0xBF,0x1F,0x00,0x41,0x00,0x00,
0x00,0x00,0x00,0x00,0x9C,0x8E,0x8F,0x50,0x60,0x96,0xB9,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x63,
0x00,0x00,0x28,0x00,0x08,0x00,0x43,0x0F,0x00,0xFC,0x00,0x00,
0x00
};
/* ET4000 BIOS mode 2Eh - 640x480x256 */
static unsigned char g640x480x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0xEA,0x8C,0xDF,0x50,0x60,0xE7,0x04,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xE3,
0x00,0x00,0x28,0x00,0x08,0x00,0x03,0x0F,0x00,0xFC,0x00,0x00,
0x00
};
/* ET4000 BIOS mode 30h - 800x600x256 */
static unsigned char g800x600x256_regs[73] = {
0x7F,0x63,0x64,0x02,0x6A,0x1D,0x77,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x5D,0x8F,0x57,0x64,0x60,0x5B,0x74,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xE3,
0x00,0x00,0x28,0x00,0x0A,0x00,0x03,0x0F,0x00,0xFC,0x00,0x00,
0x00
};
/* ET4000 BIOS mode 38h - 1024x768x256 */
static unsigned char g1024x768x256_regs[73] = {
0xA1,0x7F,0x80,0x04,0x89,0x99,0x26,0xFD,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x08,0x8A,0xFF,0x80,0x60,0x04,0x22,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xEB,
0x00,0x00,0x28,0x00,0x08,0x00,0x03,0x0F,0x00,0xBC,0x00,0x00,
0x00
};
static unsigned char g800x600x32K_regs[73] = {
0xF9,0xC7,0xC9,0x9B,0xCF,0x8F,0x78,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x5C,0x8E,0x57,0xC8,0x60,0x5B,0x75,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xEF,
0x00,0x00,0x28,0x00,0x08,0x00,0x03,0x0F,0x00,0xBC,0x00,0x00,
0x06
};
#define g800x600x64K_regs g800x600x32K_regs
static unsigned char g640x480x16M_regs[73] = {
0x27,0xEF,0xF2,0x88,0xF8,0x98,0x0B,0x3E,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0xEA,0x0C,0xDF,0xF0,0x60,0xE7,0x04,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xEF,
0x00,0x00,0x28,0x00,0x0A,0x00,0x03,0x0F,0x01,0xBC,0x00,0x00,
0x00
};
static unsigned char g640x480x32K_regs[73] = {
0xC3,0x9F,0xA1,0x85,0xA7,0x1F,0x0B,0x3E,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0xEA,0x8C,0xDF,0xA0,0x60,0xE7,0x04,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xE3,
0x00,0x00,0x28,0x00,0x08,0x00,0x03,0x0F,0x00,0xBC,0x00,0x00,
0x00
};
#define g640x480x64K_regs g640x480x32K_regs

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/*
This is for an Orchid Prodesigner II.
The 640x480 and 800x600 modes are low-end (hor. sync 35.5 kHz)
The 1024x768 modes are 60 Hz non-interlaced (hsync 48.3 kHz); be
sure to disable these if your monitor can't handle them.
(file provided by Kayvan Sylvan <kayvan@satyr.sylvan.com>)
*/
/*
( File generated by tseng3.exe )
tseng3 v1.2, Copyright (C) 1993 Tommy Frandsen, Harm Hanemaayer
and Hartmut Schirmer
Permission is granted to any individual or institution to use, copy, or
redistribute this executable so long as it is not modified and that it is
not sold for profit.
LIKE ANYTHING ELSE THAT'S FREE, TSENG3 IS PROVIDED AS IS AND COMES WITH
NO WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED. IN NO EVENT WILL
THE COPYRIGHT HOLDERS BE LIABLE FOR ANY DAMAGES RESULTING FROM THE USE OF
THIS SOFTWARE.
*/
/* Dac detection BIOS call returned an error */
#define CLOCK_VALUES { \
/* 0 */ 25175, \
/* 1 */ 28322, \
/* 2 */ 39999, \
/* 3 */ 36000, \
/* 4 */ 25177, \
/* 5 */ 28320, \
/* 6 */ 44899, \
/* 7 */ 62006 \
}
/* ET4000 HiColor BIOS mode 0x13 -- 320x200x32K : NOT SUPPORTED */
#define g320x200x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x13 -- 320x200x64K : NOT SUPPORTED */
#define g320x200x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x13 -- 320x200x16M : NOT SUPPORTED */
#define g320x200x16M_regs DISABLE_MODE
/* ET4000 BIOS mode 0x2E -- 640x480x256 */
/* Video timing: Vertical frequency : 59.9Hz
Horizontal frequency : 31.5KHz */
static unsigned char g640x480x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0xEA,0x8C,0xDF,0x50,0x60,0xE7,0x04,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xE3,
0x00,0x00,0x08,0x00,0x08,0x00,0x43,0x1F,0x00,0xBC,0x00,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x2E -- 640x480x32K : NOT SUPPORTED */
#define g640x480x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x2E -- 640x480x64K : NOT SUPPORTED */
#define g640x480x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x2E -- 640x480x16M : NOT SUPPORTED */
#define g640x480x16M_regs DISABLE_MODE
/* ET4000 BIOS mode 0x29 -- 800x600x16 */
/* Video timing: Vertical frequency : 55.9Hz
Horizontal frequency : 35.4KHz */
static unsigned char g800x600x16_regs[73] = {
0x7A,0x63,0x64,0x1D,0x68,0x9A,0x78,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x5C,0x8E,0x57,0x32,0x00,0x5B,0x75,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x0F,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x06,
0xEF,
0x00,0x00,0x08,0x00,0x08,0x00,0x43,0x1F,0x00,0xBC,0x00,0x00,
0x00
};
/* ET4000 BIOS mode 0x30 -- 800x600x256 */
/* Video timing: Vertical frequency : 55.9Hz
Horizontal frequency : 35.4KHz */
static unsigned char g800x600x256_regs[73] = {
0x7A,0x63,0x64,0x1D,0x68,0x9A,0x78,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x5C,0x8E,0x57,0x64,0x60,0x5B,0x75,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xEF,
0x00,0x00,0x08,0x00,0x08,0x00,0x43,0x1F,0x00,0xBC,0x00,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x30 -- 800x600x32K : NOT SUPPORTED */
#define g800x600x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x30 -- 800x600x64K : NOT SUPPORTED */
#define g800x600x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x30 -- 800x600x16M : NOT SUPPORTED */
/* ET4000 BIOS mode 0x37 -- 1024x768x16 */
/* Video timing: Vertical frequency : 59.9Hz
Horizontal frequency : 48.4KHz */
static unsigned char g1024x768x16_regs[73] = {
0x9B,0x7F,0x7F,0x1F,0x85,0x1B,0x26,0xF5,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x06,0x88,0xFF,0x40,0x00,0xFF,0x27,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x0F,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x06,
0x2F,
0x00,0x00,0x08,0x00,0x0A,0x00,0x43,0x1F,0x00,0xFC,0x00,0x00,
0x90
};
/* ET4000 BIOS mode 0x38 -- 1024x768x256 */
/* Video timing: Vertical frequency : 60.0Hz
Horizontal frequency : 48.4KHz */
static unsigned char g1024x768x256_regs[73] = {
0x9B,0x7F,0x7F,0x1F,0x85,0x1B,0x26,0xF5,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x06,0x88,0xFF,0x80,0x60,0xFF,0x27,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x2F,
0x00,0x00,0x08,0x00,0x0A,0x00,0x43,0x1F,0x00,0xFC,0x00,0x00,
0x90
};
/* ET4000 HiColor BIOS mode 0x38 -- 1024x768x32K : NOT SUPPORTED */
/* ET4000 HiColor BIOS mode 0x38 -- 1024x768x64K : NOT SUPPORTED */
/* ET4000 TrueColor BIOS mode 0x38 -- 1024x768x16M : NOT SUPPORTED */
/* ET4000 BIOS mode 0x3D -- 1280x1024x16 : NOT SUPPORTED */
#define g1280x1024x16_regs DISABLE_MODE
/* VESA mode 0x107 -- 1280x1024x256 : NOT SUPPORTED */
/* VESA HiColor mode 0x119 -- 1280x1024x32K : NOT SUPPORTED */
/* VESA HiColor mode 0x11A -- 1280x1024x64K : NOT SUPPORTED */
/* VESA TrueColor mode 0x11B -- 1280x1024x16M : NOT SUPPORTED */
/* --- ET4000 specific modes */
#ifdef _DYNAMIC_ONLY_
/* ET4000 BIOS mode 0x2D -- 640x350x256 */
/* Video timing: Vertical frequency : 70.1Hz
Horizontal frequency : 31.5KHz */
static unsigned char g640x350x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x83,0x85,0x5D,0x50,0x60,0x63,0xBA,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xA3,
0x00,0x00,0x08,0x00,0x08,0x00,0x43,0x1F,0x00,0xBC,0x00,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x2D -- 640x350x32K : NOT SUPPORTED */
#define g640x350x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x2D -- 640x350x64K : NOT SUPPORTED */
#define g640x350x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x2D -- 640x350x16M : NOT SUPPORTED */
#define g640x350x16M_regs DISABLE_MODE
/* ET4000 BIOS mode 0x2F -- 640x400x256 */
/* Video timing: Vertical frequency : 70.1Hz
Horizontal frequency : 31.5KHz */
static unsigned char g640x400x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x9C,0x8E,0x8F,0x50,0x60,0x96,0xB9,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x63,
0x00,0x00,0x08,0x00,0x08,0x00,0x43,0x1F,0x00,0xBC,0x00,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x2F -- 640x400x32K : NOT SUPPORTED */
#define g640x400x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x2F -- 640x400x64K : NOT SUPPORTED */
#define g640x400x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x2F -- 640x400x16M : NOT SUPPORTED */
#define g640x400x16M_regs DISABLE_MODE
#endif /* defined(_DYNAMIC_ONLY_ALL_) */

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/*
Max hor. sync: 56 Hz (1024x768 NI at 70 Hz) --HH
*/
/*********************************************************
** These register value are from a SpeedSTAR Plus V4.23 **
** **
** Oscillator frequencies (from dmode.com) : **
** **
** 25.175 28.322 75.0 72.0 80.0 44.9 50.0 65.0 **
**********************************************************/
/*
( File generated by tseng3.exe )
tseng3 v1.2, Copyright (C) 1993 Tommy Frandsen, Harm Hanemaayer
and Hartmut Schirmer
Permission is granted to any individual or institution to use, copy, or
redistribute this executable so long as it is not modified and that it is
not sold for profit.
LIKE ANYTHING ELSE THAT'S FREE, TSENG3 IS PROVIDED AS IS AND COMES WITH
NO WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED. IN NO EVENT WILL
THE COPYRIGHT HOLDERS BE LIABLE FOR ANY DAMAGES RESULTING FROM THE USE OF
THIS SOFTWARE.
*/
/* Standard VGA dac detected */
#ifndef alt
#define DAC_TYPE 0
#define CLOCK_VALUES { \
/* 0 */ 25175, \
/* 1 */ 28322, \
/* 2 */ 50181, \
/* 3 */ 61231, \
/* 4 */ 67684, \
/* 5 */ 62300, \
/* 6 */ 51760, \
/* 7 */ 59149 \
}
/* ET4000 HiColor BIOS mode 0x13 -- 320x200x32K : NOT SUPPORTED */
#define g320x200x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x13 -- 320x200x64K : NOT SUPPORTED */
#define g320x200x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x13 -- 320x200x16M : NOT SUPPORTED */
#define g320x200x16M_regs DISABLE_MODE
/* ET4000 BIOS mode 0x2E -- 640x480x256 */
/* Video timing: Vertical frequency : 72.3Hz
Horizontal frequency : 38.0KHz */
static unsigned char g640x480x256_regs[73] = {
0x66,0x4F,0x50,0x89,0x58,0x80,0x0B,0x3E,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0xEC,0x8C,0xDF,0x50,0x60,0xE7,0x04,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xEF,
0x00,0x00,0x28,0x00,0x02,0x00,0x41,0x1F,0x00,0xFC,0x01,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x2E -- 640x480x32K : NOT SUPPORTED */
#define g640x480x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x2E -- 640x480x64K : NOT SUPPORTED */
#define g640x480x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x2E -- 640x480x16M : NOT SUPPORTED */
#define g640x480x16M_regs DISABLE_MODE
/* ET4000 BIOS mode 0x29 -- 800x600x16 */
/* Video timing: Vertical frequency : 72.2Hz
Horizontal frequency : 48.1KHz */
static unsigned char g800x600x16_regs[73] = {
0x7D,0x63,0x64,0x01,0x6C,0x1A,0x98,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x69,0x80,0x57,0x32,0x00,0x59,0x7D,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x0F,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x06,
0xAB,
0x00,0x00,0x28,0x00,0x02,0x00,0x41,0x0F,0x00,0xBC,0x01,0x00,
0x00
};
/* ET4000 BIOS mode 0x30 -- 800x600x256 */
/* Video timing: Vertical frequency : 72.2Hz
Horizontal frequency : 48.1KHz */
static unsigned char g800x600x256_regs[73] = {
0x7D,0x63,0x64,0x01,0x6C,0x1A,0x98,0xF0,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x69,0x80,0x57,0x64,0x60,0x59,0x7D,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xAB,
0x00,0x00,0x28,0x00,0x02,0x00,0x41,0x0F,0x00,0xBC,0x01,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x30 -- 800x600x32K : NOT SUPPORTED */
#define g800x600x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x30 -- 800x600x64K : NOT SUPPORTED */
#define g800x600x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x30 -- 800x600x16M : NOT SUPPORTED */
/* ET4000 BIOS mode 0x37 -- 1024x768x16 */
/* Video timing: Vertical frequency : 70.0Hz
Horizontal frequency : 56.5KHz */
static unsigned char g1024x768x16_regs[73] = {
0xA1,0x7F,0x80,0x04,0x84,0x94,0x24,0xFD,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x03,0x89,0xFF,0x40,0x00,0x01,0x24,0xC3,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x0F,0x00,0x00,0x00,0x00,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x06,
0x2B,
0x00,0x00,0x28,0x00,0x00,0x00,0x41,0x0F,0x00,0xBC,0x01,0x00,
0x00
};
/* ET4000 BIOS mode 0x38 -- 1024x768x256 */
/* Video timing: Vertical frequency : 70.0Hz
Horizontal frequency : 56.4KHz */
static unsigned char g1024x768x256_regs[73] = {
0xA1,0x7F,0x80,0x04,0x84,0x94,0x24,0xFD,0x00,0x60,0x00,0x00,
0x00,0x00,0x00,0x00,0x03,0x89,0xFF,0x80,0x60,0x01,0x24,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x2B,
0x00,0x00,0x28,0x00,0x00,0x00,0x41,0x0F,0x00,0xBC,0x01,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x38 -- 1024x768x32K : NOT SUPPORTED */
/* ET4000 HiColor BIOS mode 0x38 -- 1024x768x64K : NOT SUPPORTED */
/* ET4000 TrueColor BIOS mode 0x38 -- 1024x768x16M : NOT SUPPORTED */
/* ET4000 BIOS mode 0x3D -- 1280x1024x16 : NOT SUPPORTED */
#define g1280x1024x16_regs DISABLE_MODE
/* VESA mode 0x107 -- 1280x1024x256 : NOT SUPPORTED */
/* VESA HiColor mode 0x119 -- 1280x1024x32K : NOT SUPPORTED */
/* VESA HiColor mode 0x11A -- 1280x1024x64K : NOT SUPPORTED */
/* VESA TrueColor mode 0x11B -- 1280x1024x16M : NOT SUPPORTED */
/* --- ET4000 specific modes */
#ifdef _DYNAMIC_ONLY_
/* ET4000 BIOS mode 0x2D -- 640x350x256 */
/* Video timing: Vertical frequency : 70.1Hz
Horizontal frequency : 31.5KHz */
static unsigned char g640x350x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x83,0x85,0x5D,0x50,0x60,0x63,0xBA,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0xA3,
0x00,0x00,0x28,0x00,0x00,0x00,0x41,0x0F,0x00,0xBC,0x01,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x2D -- 640x350x32K : NOT SUPPORTED */
#define g640x350x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x2D -- 640x350x64K : NOT SUPPORTED */
#define g640x350x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x2D -- 640x350x16M : NOT SUPPORTED */
#define g640x350x16M_regs DISABLE_MODE
/* ET4000 BIOS mode 0x2F -- 640x400x256 */
/* Video timing: Vertical frequency : 70.1Hz
Horizontal frequency : 31.5KHz */
static unsigned char g640x400x256_regs[73] = {
0x5F,0x4F,0x50,0x82,0x54,0x80,0xBF,0x1F,0x00,0x40,0x00,0x00,
0x00,0x00,0x00,0x00,0x9C,0x8E,0x8F,0x50,0x60,0x96,0xB9,0xAB,
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,
0x0C,0x0D,0x0E,0x0F,0x01,0x00,0x0F,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0F,0xFF,
0x03,0x01,0x0F,0x00,0x0E,
0x63,
0x00,0x00,0x28,0x00,0x00,0x00,0x41,0x0F,0x00,0xBC,0x01,0x00,
0x00
};
/* ET4000 HiColor BIOS mode 0x2F-- 640x400x32K : NOT SUPPORTED */
#define g640x400x32K_regs DISABLE_MODE
/* ET4000 HiColor BIOS mode 0x2F-- 640x400x64K : NOT SUPPORTED */
#define g640x400x64K_regs DISABLE_MODE
/* ET4000 TrueColor BIOS mode 0x2F-- 640x400x16M : NOT SUPPORTED */
#define g640x400x16M_regs DISABLE_MODE
#endif /* defined(_DYNAMIC_ONLY_ALL_) */

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/*
** tseng3.c - get ET4000 graphics register values
** Copyright (C) 1993 Tommy Frandsen, Harm Hanemaayer, Hartmut Schirmer
**
** This program is free software;
**
** Permission is granted to any individual or institution to use, copy,
** or redistribute this executable so long as it is not modified and
** that it is not sold for profit.
**
** LIKE ANYTHING ELSE THAT'S FREE, TSENG3 IS PROVIDED AS IS AND
** COMEs WITH NO WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED.
** IN NO EVENT WILL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY DAMAGES
** RESULTING FROM THE USE OF THIS SOFTWARE.
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <conio.h>
#include <dos.h>
#include <stdarg.h>
/* VGA index register ports */
#define CRT_I 0x3D4 /* CRT Controller Index (mono: 0x3B4) */
#define ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
#define GRA_I 0x3CE /* Graphics Controller Index */
#define SEQ_I 0x3C4 /* Sequencer Index */
#define PEL_IW 0x3C8 /* PEL Write Index */
/* VGA data register ports */
#define CRT_D 0x3D5 /* CRT Controller Data Register (mono: 0x3B5) */
#define ATT_R 0x3C1 /* Attribute Controller Data Read Register */
#define GRA_D 0x3CF /* Graphics Controller Data Register */
#define SEQ_D 0x3C5 /* Sequencer Data Register */
#define MIS_R 0x3CC /* Misc Output Read Register */
#define MIS_W 0x3C2 /* Misc Output Write Register */
#define IS1_R 0x3DA /* Input Status Register 1 (mono: 0x3BA) */
#define PEL_D 0x3C9 /* PEL Data Register */
/* VGA indexes max counts */
#define CRT_C 24 /* 24 CRT Controller Registers */
#define ATT_C 21 /* 21 Attribute Controller Registers */
#define GRA_C 9 /* 9 Graphics Controller Registers */
#define SEQ_C 5 /* 5 Sequencer Registers */
#define MIS_C 1 /* 1 Misc Output Register */
#define EXT_C 17 /* 11 SVGA Extended Registers */
/* VGA registers saving indexes */
#define CRT 0 /* CRT Controller Registers start */
#define ATT CRT+CRT_C /* Attribute Controller Registers start */
#define GRA ATT+ATT_C /* Graphics Controller Registers start */
#define SEQ GRA+GRA_C /* Sequencer Registers */
#define MIS SEQ+SEQ_C /* General Registers */
#define EXT MIS+MIS_C /* SVGA Extended Registers */
#define TOTAL EXT+EXT_C /* # or registers values */
unsigned char vga_regs[TOTAL];
static int do_all = 0;
FILE *output = NULL;
static int save_extregs;
void port_out(unsigned char value, unsigned short port)
{
asm mov dx,port
asm mov al,value
asm out dx,al
}
unsigned char port_in(unsigned short port)
{
asm mov dx,port
asm in al,dx
return (_AL);
}
int dactype(void)
{
union REGS cpu_regs;
cpu_regs.x.ax=0x10F1;
cpu_regs.x.bx=0x2EFF;
int86(0x10, &cpu_regs, &cpu_regs);
if (cpu_regs.x.ax != 0x0010)
return (-1);
else
return (cpu_regs.h.bl);
}
int read_dac(int addr)
{
inp(0x3c8);
inp(0x3c6);
inp(0x3c6);
inp(0x3c6);
inp(0x3c6);
while (addr)
--addr,inp(0x3c6);
addr = inp(0x3c6);
return addr;
}
int write_dac(int addr,int value)
{
inp(0x3c8);
inp(0x3c6);
inp(0x3c6);
inp(0x3c6);
inp(0x3c6);
while (addr)
--addr,inp(0x3c6);
outp(0x3c6,value);
return read_dac(addr);
}
int read_ext_dac(int addr)
{
write_dac(1,addr);
write_dac(2,0);
return read_dac(3);
}
void puts2(char *s) {
if (output != NULL)
fprintf(output, "%s\n", s);
while (*s != '\0') {
if (*s == '\n') putch('\r');
putch (*(s++));
}
putch('\r'); putch('\n');
}
int printf2(char *fmt, ...)
{
va_list argptr;
char str[140], *s;
int cnt;
va_start( argptr, fmt );
if (output != NULL)
vfprintf(output, fmt, argptr);
cnt = vsprintf( str, fmt, argptr );
s = str;
while (*s) {
switch (*s) {
case '\n' : putch('\r');
break;
case '\t' : cprintf("%*s", 8-((wherex()-1)&7), "");
++s;
continue;
}
putch(*(s++));
}
va_end( argptr );
return( cnt );
}
void get_dac(void)
{
int dac;
dac = dactype();
switch (dac)
{
case -1:
printf2 ("/* Dac detection BIOS call returned an error */\n");
break;
case 0:
printf2 ("/* Standard VGA dac detected */\n");
printf2 ("#define DAC_TYPE 0\n");
break;
case 1:
printf2 ("/* Sierra SC1148x HiColor dac detected */\n");
printf2 ("#define DAC_TYPE 1\n");
break;
case 2:
printf2 ("/* Diamond Speedstar 24 24bit dac or Sierra Mark2/Mark3 dac detected */\n");
break;
case 3:
printf2 ("/* AT&T ATT20c491/2 15/16/24 bit dac detected */\n");
printf2 ("#define DAC_TYPE 9\n");
break;
case 4:
printf2 ("/* AcuMos ADAC1 15/16/24 bit dac detected */\n");
break;
case 8:
printf2 ("/* Music 15/16/24 bit dac (AT&T compatible) detected */\n");
printf2 ("#define DAC_TYPE 9\n");
break;
default: { /* use alternate method */
int cmd = read_dac(0);
write_dac(0,cmd | 0x10);
if (read_ext_dac(0) == 0x44) {
printf2 ("/* SGS-Thomson STG170x 15/16/24 dac detected */\n");
save_extregs = 1;
}
else
printf2 ("/* Unknown HiColor dac (%d) detected */\n", dac);
break;
}
}
}
#define TickTime (1.0/1193182.0)
#define init_timer() do { \
asm mov al, 034h; \
asm out 043h, al; \
asm xor al, al; \
asm out 040h, al; \
asm out 040h, al; \
} while(0)
#define ReadTimer(dst) do { \
asm { mov al, 4; \
out 43h, al; \
in al, 40h; \
mov bl, al; \
in al, 40h; \
mov ah, al; \
mov al, bl; \
not ax } \
(dst) = _AX; \
} while (0);
#define _wait_(ID,VAL) \
w_##ID##1: \
asm in al, dx; \
asm test al, VAL; \
asm jne w_##ID##1; \
w_##ID##2: \
asm in al, dx; \
asm test al, VAL; \
asm je w_##ID##2
#define wait_horizontal(ID,port) do { _DX=(port); _wait_(ID##ch,8);} while(0)
#define wait_vertical(ID,port) do { _DX=(port); _wait_(ID##cv,1);} while(0)
#define __loop__(ID,port,loops,msk) do { \
register int cnt = (loops); \
_DX=(port); \
do { \
_wait_(ID,msk); \
} while (--cnt > 0); \
} while(0)
#define loop_vertical(ID,port,loops) __loop__(ID##cv,(port),(loops),1)
int interlaced(void) {
return (vga_regs[EXT+5] & 0x80) ? 1 : 0;
}
int calc_vtotal(void) {
int total;
total = (vga_regs[EXT+5]&2) ? 1024 : 0;
switch (vga_regs[CRT+7]&0x21) {
case 0x01 : total += 256; break;
case 0x20 : total += 512; break;
case 0x21 : total += 768; break;
}
total += vga_regs[CRT+6];
return total + 2;
}
double measure_horizontal(void)
{
short start, stop;
long diff;
disable();
init_timer();
wait_horizontal(mv0,0x3da);
wait_vertical(mv0,0x3da);
ReadTimer(start);
loop_vertical(mv, 0x3da, 200);
ReadTimer(stop);
enable();
diff = stop-start;
if (diff < 0) diff += 65536L;
return 200/(TickTime*((double)diff));
}
#define ASK_CONT 0
#define ASK_SKIP 1
#define ASK_ALL 2
int ask(char *expl)
{
int ch;
cprintf("\r\n\n"
"ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r\n"
"º WARNING: Improper use of this program may destroy your monitor º\r\n"
"ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ\r\n\n"
"%s\r\n\n"
"Type SPACE to skip, ESC to cancel program, RETURN to continue ... ",
expl);
do {
ch = getch();
if (ch == 27) exit(1);
switch (ch) {
case 27 : exit(1);
case ' ' : return ASK_SKIP;
case 'A' : return ASK_ALL;
case '\r': return ASK_CONT;
}
} while (1);
}
void get_clocks(void)
{
union REGS cpu_regs;
unsigned char temp;
int i;
double clock[8], horzbase, baseosc;
if (!do_all)
switch (ask("Measure clock frequencies")) {
case ASK_SKIP : return;
case ASK_ALL : do_all = 1; break;
default : break;
}
cpu_regs.h.ah = 0x00;
cpu_regs.h.al = 0x13;
int86(0x10, &cpu_regs, &cpu_regs);
port_out(0x03, 0x3BF); /* Unprotect ET4000 registers */
port_out(0xA0, 0x3D8);
port_out(0x00, ATT_IW); /* disable video */
port_out(7, SEQ_I); /* devide by 4 */
temp = port_in(SEQ_D);
port_out(temp | 0x41, SEQ_D);
baseosc = 25175; /* Base frequency */
switch (temp & 0x41) {
case 0x41 : baseosc *= 4; break;
case 0x40 : baseosc *= 2; break;
}
clock[0] = baseosc;
clock[1] = baseosc * 28322.0 / 25175.0;
horzbase = measure_horizontal();
for (i=2; i < 8; ++i) {
temp = (port_in(MIS_R) & 0xF3) | ((i&3)<<2);
port_out(temp, MIS_W);
port_out(0x34, CRT_I);
temp = (port_in(CRT_D) & 0xFD) | ((i&4)>>1);
port_out(temp, CRT_D);
clock[i] = baseosc*measure_horizontal()/horzbase;
}
cpu_regs.h.ah = 0x00;
cpu_regs.h.al = 0x03;
int86(0x10, &cpu_regs, &cpu_regs);
printf2("\n#define CLOCK_VALUES {\t\\\n");
for (i = 0; i < 8; ++i)
printf2("\t/* %d */ %5.0f%s\t\\\n", i, clock[i],(i==7?"":","));
printf2("\t}\n");
}
void one_mode(int vesa_mode, int mode, int colbits, int funny_card)
{
union REGS cpu_regs;
int i, skip = 0, modeok = 0;
int x=0, y, col, size;
char resol[100], colors[100], *desc;
char *verttxt;
double vertical, horizontal;
switch (mode) {
case 0x13: x = 320; y = 200; break;
case 0x25: x = 640; y = 480; break;
case 0x29: x = 800; y = 600; break;
case 0x2d: x = 640; y = 350; break;
case 0x2e: x = 640; y = 480; break;
case 0x2f: x = 640; y = 400; break;
case 0x30: x = 800; y = 600; break;
case 0x37: x = 1024; y = 768; break;
case 0x38: x = 1024; y = 768; break;
case 0x3d: x = 1280; y = 1024; break;
default : switch (vesa_mode) {
case 0x107:
case 0x119:
case 0x11a:
case 0x11b: x = 1280; y = 1024; break;
default : return;
}
break;
}
col = (1<<colbits);
size = (int)((((unsigned long) x) * ((unsigned long) y)) >> 10);
if (col == 16) size >>= 2;
switch (colbits) {
case 15: size*=2; strcpy(colors, "32K"); desc = "HiColor "; break;
case 16: size*=2; strcpy(colors, "64K"); desc = "HiColor "; break;
case 24: size*=3; strcpy(colors, "16M"); desc = "TrueColor "; break;
default: sprintf(colors, "%d", col); desc = ""; break;
}
sprintf(resol, "%dx%dx%s", x, y, colors);
if (!do_all) {
char expl[100];
sprintf(expl, "BIOS mode 0x%2X : %s", mode, resol);
switch(ask(expl)) {
case ASK_SKIP : skip = 1; break;
case ASK_ALL : do_all = 1; break;
default : break;
}
}
if (!skip) {
/* First try VESA mode */
if (vesa_mode != 0) {
cpu_regs.x.ax = 0x4f02;
cpu_regs.x.bx = vesa_mode;
int86(0x10, &cpu_regs, &cpu_regs);
modeok = (cpu_regs.x.ax == 0x004f);
}
/* Try std ET4000 mode numbers if VESA failed */
if (!modeok && mode != 0) {
switch (colbits)
{
case 15:
case 16:
cpu_regs.x.ax=0x10F0;
cpu_regs.h.bl=mode;
break;
case 24:
switch (funny_card)
{
case 1:
cpu_regs.x.ax=0x10E0;
cpu_regs.h.bl=0x2e;
break;
case 2:
cpu_regs.x.ax=0x10f0;
cpu_regs.h.bl=0x3e;
break;
case 0:
default:
cpu_regs.x.ax=0x10F0;
cpu_regs.h.bh=mode;
cpu_regs.h.bl=0xFF;
break;
}
break;
case 0:
default:
cpu_regs.h.ah = 0x00;
cpu_regs.h.al = mode;
break;
}
int86(0x10, &cpu_regs, &cpu_regs);
modeok = !( (colbits > 8 && cpu_regs.x.ax != 0x0010)
||(colbits <=8 && cpu_regs.x.ax == mode ) );
vesa_mode = 0;
}
if (modeok) {
/* get VGA register values */
for (i = 0; i < CRT_C; i++) {
port_out(i, CRT_I);
vga_regs[CRT+i] = port_in(CRT_D);
}
for (i = 0; i < ATT_C; i++) {
if (col == 16 && i < 16)
vga_regs[ATT+i] = i;
else {
port_in(IS1_R);
port_out(i, ATT_IW);
vga_regs[ATT+i] = port_in(ATT_R);
}
}
for (i = 0; i < GRA_C; i++) {
if (i==1 && col == 16)
vga_regs[GRA+i] = 0x0F;
else {
port_out(i, GRA_I);
vga_regs[GRA+i] = port_in(GRA_D);
}
}
for (i = 0; i < SEQ_C; i++) {
port_out(i, SEQ_I);
vga_regs[SEQ+i] = port_in(SEQ_D);
}
vga_regs[MIS] = port_in(MIS_R);
/* get extended CRT registers */
for (i = 0; i < 8; i++) {
port_out(0x30+i, CRT_I);
vga_regs[EXT+i] = port_in(CRT_D);
}
port_out(0x3f , CRT_I);
vga_regs[EXT+8] = port_in(CRT_D);
/* get extended sequencer register */
port_out(7, SEQ_I);
vga_regs[EXT+9] = port_in(SEQ_D);
/* get some other ET4000 specific registers */
vga_regs[EXT+10] = port_in(0x3c3);
vga_regs[EXT+11] = port_in(0x3cd);
/* get extended attribute register */
port_in(IS1_R); /* reset flip flop */
port_out(0x16, ATT_IW);
vga_regs[EXT+12] = port_in(ATT_R);
if (save_extregs) { /* copy stg170x extended info */
vga_regs[EXT+13] = read_dac(0);
write_dac(0,vga_regs[EXT+13] | 0x10);
vga_regs[EXT+14] = read_ext_dac(3);
vga_regs[EXT+15] = read_ext_dac(4);
vga_regs[EXT+16] = read_ext_dac(5);
}
/* Measure video timing */
horizontal = measure_horizontal();
/* switch back to text mode */
cpu_regs.h.ah = 0x00;
cpu_regs.h.al = 0x03;
int86(0x10, &cpu_regs, &cpu_regs);
}
}
if (vesa_mode)
printf2("\n/* VESA %smode 0x%03X", desc, vesa_mode);
else
printf2("\n/* ET4000 %sBIOS mode 0x%02X", desc, mode);
printf2(" -- %s", resol);
if ( skip || !modeok) {
printf2(" : NOT SUPPORTED */\n");
if (size <= 1024)
printf2("#define g%s_regs DISABLE_MODE\n", resol);
return;
}
printf2(" */\n");
/* can't always treat 15 and 16 bit modes the same! */
if (colbits == 16 && !save_extregs) {
printf2("#define g%s_regs g%dx%dx32K_regs\n", resol, x, y);
return;
}
verttxt = interlaced() ? " (interlaced)" : "";
vertical = horizontal / calc_vtotal();
printf2("/* Video timing:\tVertical frequency : %4.1fHz%s\n",
vertical, verttxt);
printf2("\t\t\tHorizontal frequency : %4.1fKHz */\n", horizontal/1000.0);
printf2("static unsigned char g%s_regs[%d] = {\n ", resol, TOTAL);
for (i = 0; i < CRT_C; i++)
printf2("%s0x%02X,", (i==12?"\n ":""), vga_regs[CRT+i]);
printf2("\n ");
for (i = 0; i < ATT_C; i++)
printf2("%s0x%02X,", (i==12?"\n ":""), vga_regs[ATT+i]);
printf2("\n ");
for (i = 0; i < GRA_C; i++)
printf2("0x%02X,",vga_regs[GRA+i]);
printf2("\n ");
for (i = 0; i < SEQ_C; i++)
printf2("0x%02X,",vga_regs[SEQ+i]);
printf2("\n 0x%02X,",vga_regs[MIS]);
printf2("\n 0x%02X",vga_regs[EXT]);
for (i = 1; i < EXT_C; i++)
printf2(",%s0x%02X", (i==12?"\n ":""), vga_regs[i+EXT]);
printf2("\n};\n");
}
void usage(void) {
cputs("tseng3 <output_file> [SS24]");
exit(1);
}
void main(int argc, char* argv[])
{
int funny_card = 0;
if (argc >= 2)
output = fopen(argv[1], "w");
if (output != NULL)
fputs("/*\n ( File generated by tseng3.exe )\n\n", output);
puts2("tseng3 v1.2, Copyright (C) 1993 Tommy Frandsen, Harm Hanemaayer");
puts2("and Hartmut Schirmer\n");
puts2("Permission is granted to any individual or institution to use, copy, or");
puts2("redistribute this executable so long as it is not modified and that it is");
puts2("not sold for profit.\n");
puts2("LIKE ANYTHING ELSE THAT'S FREE, TSENG3 IS PROVIDED AS IS AND COMES WITH");
puts2("NO WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED. IN NO EVENT WILL");
puts2("THE COPYRIGHT HOLDERS BE LIABLE FOR ANY DAMAGES RESULTING FROM THE USE OF");
puts2("THIS SOFTWARE.");
if (output != NULL)
fputs("*/\n", output);
puts2("");
if (argc >= 2 && output == NULL)
usage();
if (argc>=3)
funny_card = (strcmp("SS24", argv[2]) == 0) ? 1 : 2;
get_dac();
get_clocks();
one_mode(0x10d, 0x13, 15, funny_card); /* 320x200x32K */
one_mode(0x10e, 0x13, 16, funny_card); /* 320x200x64K */
one_mode(0x10f, 0x13, 24, funny_card); /* 320x200x16M */
one_mode(0x101, 0x2e, 8, funny_card); /* 640x480x256 */
one_mode(0x110, 0x2e, 15, funny_card); /* 640x480x32K */
one_mode(0x111, 0x2e, 16, funny_card); /* 640x480x64K */
one_mode(0x112, 0x2e, 24, funny_card); /* 640x480x16M */
one_mode(0x102, 0x29, 4, funny_card); /* 800x600x16 */
one_mode(0x103, 0x30, 8, funny_card); /* 800x600x256 */
one_mode(0x113, 0x30, 15, funny_card); /* 800x600x32K */
one_mode(0x114, 0x30, 16, funny_card); /* 800x600x64K */
one_mode(0x115, 0x30, 24, funny_card); /* 800x600x16M */
one_mode(0x104, 0x37, 4, funny_card); /* 1024x768x16 */
one_mode(0x105, 0x38, 8, funny_card); /* 1024x768x256 */
one_mode(0x116, 0x38, 15, funny_card); /* 1024x768x32K */
one_mode(0x117, 0x38, 16, funny_card); /* 1024x768x64K */
one_mode(0x118, 0x38, 24, funny_card); /* 1024x768x16M */
one_mode(0x106, 0x3D, 4, funny_card); /* 1280x1024x16 */
one_mode(0x107, 0x00, 8, funny_card); /* 1280x1024x256 */
one_mode(0x119, 0x00, 15, funny_card); /* 1280x1024x32K */
one_mode(0x11a, 0x00, 16, funny_card); /* 1280x1024x64K */
one_mode(0x11b, 0x00, 24, funny_card); /* 1280x1024x16M */
puts2("\n/* --- ET4000 specific modes */\n#ifdef _DYNAMIC_ONLY_");
one_mode(0x000, 0x2d, 8, funny_card); /* 640x350x256 */
one_mode(0x000, 0x2d, 15, funny_card); /* 640x350x32K */
one_mode(0x000, 0x2d, 16, funny_card); /* 640x350x64K */
one_mode(0x000, 0x2d, 24, funny_card); /* 640x350x16M */
one_mode(0x100, 0x2f, 8, funny_card); /* 640x400x256 */
one_mode(0x000, 0x2f, 15, funny_card); /* 640x400x32K */
one_mode(0x000, 0x2f, 16, funny_card); /* 640x400x64K */
one_mode(0x000, 0x2f, 24, funny_card); /* 640x400x16M */
puts2("\n#endif /* defined(_DYNAMIC_ONLY_ALL_) */\n");
}

BIN
obsolete/et4000/tseng3.exe Normal file
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152
obsolete/jump/jump.funcs Normal file
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@ -0,0 +1,152 @@
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294
obsolete/jump/jump.ignore Normal file
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@ -0,0 +1,294 @@
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00000000 T ___svgalib_driver24_setpixel libvga driver
00000000 T ___svgalib_driver24p_setpixel libvga driver
00000000 T ___svgalib_driver24_getpixel libvga driver
00000000 T ___svgalib_driver24p_getpixel libvga driver
00000000 T ___svgalib_driver24_hline libvga driver
00000000 T ___svgalib_driver24p_hline libvga driver
00000000 T ___svgalib_driver24_fillbox libvga driver
00000000 T ___svgalib_driver24p_fillbox libvga driver
00000000 T ___svgalib_driver24_putbox libvga driver
00000000 T ___svgalib_driver24p_putbox libvga driver
00000000 T ___svgalib_driver24_putbox32 libvga driver
00000000 T ___svgalib_driver24_getbox libvga driver
00000000 T ___svgalib_driver24p_getbox libvga driver
00000000 T ___svgalib_driver24_putboxmask libvga driver
00000000 T ___svgalib_driver24_putboxpart libvga driver
00000000 T ___svgalib_driver24p_putboxpart libvga driver
00000000 T ___svgalib_driver24_getboxpart libvga driver
00000000 T ___svgalib_driver24p_getboxpart libvga driver
00000000 T ___svgalib_driver24_copybox libvga driver
00000000 T ___svgalib_driver24a_copybox libvga driver
00000000 T ___svgalib_driver32_setpixel libvga driver
00000000 T ___svgalib_driver32p_setpixel libvga driver
00000000 T ___svgalib_driver32_getpixel libvga driver
00000000 T ___svgalib_driver32p_getpixel libvga driver
00000000 T ___svgalib_driver32_hline libvga driver
00000000 T ___svgalib_driver32p_hline libvga driver
00000000 T ___svgalib_driver32_fillbox libvga driver
00000000 T ___svgalib_driver32p_fillbox libvga driver
00000000 T ___svgalib_driver32_putbox libvga driver
00000000 T ___svgalib_driver32p_putbox libvga driver
00000000 T ___svgalib_driver32_getbox libvga driver
00000000 T ___svgalib_driver32p_getbox libvga driver
00000000 T ___svgalib_driver32_putboxmask libvga driver
00000000 T ___svgalib_driver32_putboxpart libvga driver
00000000 T ___svgalib_driver32p_putboxpart libvga driver
00000000 T ___svgalib_driver32_getboxpart libvga driver
00000000 T ___svgalib_driver32p_getboxpart libvga driver
00000000 T ___svgalib_driver32_copybox libvga driver
00000000 T ___svgalib_driverplanar256_nothing libvga driver
00000000 T ___svgalib_driverplanar256_putbox libvga driver
00000000 T ___svgalib_driverplanar16_nothing libvga driver
00000000 T ___svgalib_driver_setread libvga driver
00000000 T ___svgalib_driver_setwrite libvga driver
00000000 T ___svgalib_driver8p_putboxmask libvga driver
00000000 T ___svgalib_driver8p_copybox libvga driver
00000000 T ___svgalib_driver16p_putboxmask libvga driver
00000000 T ___svgalib_driver16p_copybox libvga driver
00000000 T ___svgalib_driver24p_putboxmask libvga driver
00000000 T ___svgalib_driver24p_copybox libvga driver
00000000 T ___svgalib_driver32p_putboxmask libvga driver
00000000 T ___svgalib_driver32p_copybox libvga driver
00000000 T ___svgalib_memcpy4to3 libvga mem
00000000 T ___svgalib_memcpy32shift8 libvga mem
00000000 C ___svgalib_oldvtmode libvga vga
00000000 C ___svgalib_runinbackground libvga vga
00000000 C ___svgalib_graph_mem_linear_orginal libvga vga
00000000 C ___svgalib_graph_mem_linear_check libvga vga
00000000 C ___svgalib_linear_memory_size libvga vga
00000000 C ___svgalib_linearframebuffer libvga vgamisc
00000000 C ___svgalib_nonaccel_fillbox libvga grlib
00000000 D ___svgalib_apm_driverspecs libvga apm
00000000 D ___svgalib_default_mode libvga vga
00000000 D ___svgalib_nosigint libvga vga
00000000 D ___svgalib_m_ignore_dx libvga mouse/mouse
00000000 D ___svgalib_m_ignore_dy libvga mouse/mouse
00000000 D ___svgalib_m_ignore_dz libvga mouse/mouse
00000000 C ___svgalib_mouse_eventhandler libvga mouse/mouse
00000000 D ___svgalib_graph_base libvga vga
00000000 D ___svgalib_novga libvga vga
00000000 D ___svgalib_secondary libvga vga
00000000 T ___svgalib_pci_find_vendor_vga libvga vgapci
00000000 D ___svgalib_nv3_driverspecs libvga nv3
00000000 D ___svgalib_et6000_driverspecs libvga et6000
00000000 C ___svgalib_keyboard_eventhandler libvga keyboard/keyboard
00000000 D ___svgalib_vesa_driverspecs libvga vesa
00000000 T ___svgalib_vm86old libvga lrmi
00000000 T ___svgalib_LRMI_alloc_real libvga lrmi
00000000 T ___svgalib_LRMI_free_real libvga lrmi
00000000 K ___svgalib_LRMI__inline_asm libvga lrmi
00000000 T ___svgalib_LRMI_init libvga lrmi
00000000 T ___svgalib_LRMI_call libvga lrmi
00000000 T ___svgalib_LRMI_int libvga lrmi
00000000 D ___svgalib_textprog libvga vga
00000000 C ___svgalib_TextProg_argv libvga vga
00000000 C ___svgalib_TextProg libvga vga
00000000 D ___svgalib_mx_driverspecs libvga mx

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00000004 C _graph_mem libvga vga
0000005C C _currentcontext libvgagl grlib
00000004 D _gl_font8x8 libvgagl font8x8

1
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Please read 'man 7 svgalib.mach32'

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Mach64 driver changes log:
--------------------------
April 11, 1998 (Michael Weller)
VGA Emulation should be used to avoid MACH64 code in get_lut
(and elsewhere?)
March 17, 1996 (Asad Hanif)
NON FUNCTIONAL DRIVER sent for inclusion in 1.2.10
It doesn't seem to quite work. Its hardcoded to 640x480x256@60hz for
a WINTURBO 2mbVRAM and 68860 ramdac - with the 18818 clock.
The screen has vertical bars thru it... each 64k chunk is a little offset
and its full of crap. I can't seem to track the problem down. I checked
the CRTC registers, and dac programming. They are similar to what I got
from ATI and based on what I yanked from XFree86.
Help.
Added dac handling code to vgapal.c.
Didn't work so I stripped it clean. Removed clock programming...
fixed the dac to 68860 and clock to 8 - the default clock setting.
Based code on combination of ATI's SDK and the mach64 x server.
Went from a.out to elf.
Discovered a hell of a lof of segfaults. Due to my attempts to be nice
and unmap and free any mapped/allocated ram... uncommented worked fine.
Nov 18, 1995 (Asad Hanif)
Re-synced to pre 1.2.9 from 1.2.7
Sept 25, 1995 (Asad Hanif)
So I'm lazy (actually busy)
Well... I got the updated SDK from ATI. Updated the autodetect function
to reflect the SDK recommendations. I'm gonna avoid using the Extended
vga registers to try and maintain compatability with the CT/ET. So all
work will be done with the Mach64 controller thingy.
It now downloads all the necessary data from the rom.
Sept 2, 1995 (Asad Hanif)
Stuck in a register dumper so I know what I see.
It's still a vga driver.
Aug 30, 1995 (Asad Hanif)
This files was created to log all the changes made to svgalib-1.2.7 in
order to incorporate an ATI Mach 64 driver.
libvga.h: The Mach64 has 32 bit registers. The libvga.h doesn't
have code for inl and outl. These were added.
vga.h: Well.. gotta tell it there's a new driver.
Mach64 = 13 ooohh.. lucky number. But its actually
the 14th driver-- if you count from 0. :)
vga.c: Added the driver to the list.
config.h: Added some INCLUDE_MACH64_...
driver.h: Added the extern driver specs thingy.
Makefile.aout: stuck a line in their about mach64.c
mach64.regs: Named register list.
mach64.h: Header file.
mach64.c: Driver.
mach64.CHANGES: You're look at it.
Genesis

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mach32info: mach32info.c
cc -Wall -O2 -s mach32info.c -o mach32info
clean:
rm -f mach32info *.o

64
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# These are the definitions for the standard modes that the driver uses
# as they are allowed in the EEPROM. If one mode is slightly shifted
# on your screen, you can take the info here and slightly adjust sync
# timing for correct alignment.
# 640x480 31.406kHz 59.82Hz
define 640x480x256 640x480x32K 640x480x64K 640x480x16M 640x480x16M32
:20 640 664 675 800 480 491 493 524 -hsync -vsync
# 640x480 37.736kHz 72.57Hz
define 640x480x256 640x480x32K 640x480x64K 640x480x16M 640x480x16M32
:9 640 664 668 848 480 489 491 519 -hsync -vsync
# 800x600 31.492kHz 89.72Hz Interlaced
define 800x600x256 800x600x32K 800x600x64K 800x600x16M 800x600x16M32
:31 800 888 903 1064 600 611 629 704 interlace +hsync -vsync
# 800x600 33.835kHz 96.39Hz Interlaced
define 800x600x256 800x600x32K 800x600x64K 800x600x16M 800x600x16M32
:3 800 880 895 1064 600 611 629 704 interlace +hsync +vsync
# 800x600 35.156kHz 56.25Hz
define 800x600x256 800x600x32K 800x600x64K 800x600x16M 800x600x16M32
:3 800 824 832 1024 600 601 603 624 -hsync +vsync
# 800x600 37.879kHz 60.32Hz
define 800x600x256 800x600x32K 800x600x64K 800x600x16M 800x600x16M32
:12 800 840 855 1056 600 604 606 627 +hsync +vsync
# 800x600 44.544kHz 70.04Hz
define 800x600x256 800x600x32K 800x600x64K 800x600x16M 800x600x16M32
:7 800 808 825 1008 600 609 611 635 -hsync -vsync
# 800x600 48.044kHz 72.14Hz
define 800x600x256 800x600x32K 800x600x64K 800x600x16M 800x600x16M32
:4 800 856 870 1048 600 637 639 665 +hsync +vsync
# 1024x768 35.522kHz 86.64Hz Interlaced
define 1024x768x256 1024x768x32K 1024x768x64K 1024x768x16M 1024x768x16M32
:7 1024 1040 1061 1264 768 769 787 820 interlace +hsync +vsync
# 1024x768 48.363kHz 60.00Hz
define 1024x768x256 1024x768x32K 1024x768x64K 1024x768x16M 1024x768x16M32
:15 1024 1048 1064 1344 768 771 773 805 -hsync -vsync
# 1024x768 56.476kHz 70.07Hz
define 1024x768x256 1024x768x32K 1024x768x64K 1024x768x16M 1024x768x16M32
:14 1024 1072 1093 1392 768 776 778 815 -hsync +vsync
# 1024x768 58.230kHz 72.245Hz
define 1024x768x256 1024x768x32K 1024x768x64K 1024x768x16M 1024x768x16M32
:14 1024 1056 1072 1328 768 771 773 805 -hsync -vsync
# 1024x768 53.879kHz 66.03Hz
define 1024x768x256 1024x768x32K 1024x768x64K 1024x768x16M 1024x768x16M32
:14 1024 1048 1064 1288 768 771 773 805 -hsync -vsync
# 1280x1024 50.000kHz 87.03Hz Interlaced
define 1280x1024x256 1280x1024x32K 1280x1024x64K 1280x1024x16M 1280x1024x16M32
:11 1280 1360 1369 1600 1024 1074 1092 1148 interlace +hsync +vsync
# 1280x1024 50.000kHz 94.97Hz Interlaced
define 1280x1024x256 1280x1024x32K 1280x1024x64K 1280x1024x16M 1280x1024x16M32
:11 1280 1360 1369 1600 1024 1034 1052 1052 interlace +hsync +vsync

1122
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File diff suppressed because it is too large Load diff

1091
obsolete/mach/mach64.c Normal file
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File diff suppressed because it is too large Load diff

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/* ATI Mach64 Driver for SVGALIB - (Driver (C) 1996 Asad F. Hanif)
Ye olde defines
*/
/* Mach64 io and memory mapped registers */
/* ripped from ati sdk */
/* NON-GUI IO MAPPED Registers */
#define ioCRTC_H_TOTAL_DISP 0x02EC
#define ioCRTC_H_SYNC_STRT_WID 0x06EC
#define ioCRTC_V_TOTAL_DISP 0x0AEC
#define ioCRTC_V_SYNC_STRT_WID 0x0EEC
#define ioCRTC_VLINE_CRNT_VLINE 0x12EC
#define ioCRTC_OFF_PITCH 0x16EC
#define ioCRTC_INT_CNTL 0x1AEC
#define ioCRTC_GEN_CNTL 0x1EEC
#define ioOVR_CLR 0x22EC
#define ioOVR_WID_LEFT_RIGHT 0x26EC
#define ioOVR_WID_TOP_BOTTOM 0x2AEC
#define ioCUR_CLR0 0x2EEC
#define ioCUR_CLR1 0x32EC
#define ioCUR_OFFSET 0x36EC
#define ioCUR_HORZ_VERT_POSN 0x3AEC
#define ioCUR_HORZ_VERT_OFF 0x3EEC
#define ioSCRATCH_REG0 0x42EC
#define ioSCRATCH_REG1 0x46EC
#define ioCLOCK_SEL_CNTL 0x4AEC
#define ioBUS_CNTL 0x4EEC
#define ioMEM_CNTL 0x52EC
#define ioMEM_VGA_WP_SEL 0x56EC
#define ioMEM_VGA_RP_SEL 0x5AEC
#define ioDAC_REGS 0x5EEC
#define ioDAC_CNTL 0x62EC
#define ioGEN_TEST_CNTL 0x66EC
#define ioCONFIG_CNTL 0x6AEC
#define ioCONFIG_CHIP_ID 0x6EEC
#define ioCONFIG_STAT0 0x72EC
#define ioCONFIG_STAT1 0x76EC
/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
#define mCRTC_H_TOTAL_DISP 0x0000
#define mCRTC_H_SYNC_STRT_WID 0x0004
#define mCRTC_V_TOTAL_DISP 0x0008
#define mCRTC_V_SYNC_STRT_WID 0x000C
#define mCRTC_VLINE_CRNT_VLINE 0x0010
#define mCRTC_OFF_PITCH 0x0014
#define mCRTC_INT_CNTL 0x0018
#define mCRTC_GEN_CNTL 0x001C
#define mOVR_CLR 0x0040
#define mOVR_WID_LEFT_RIGHT 0x0044
#define mOVR_WID_TOP_BOTTOM 0x0048
#define mCUR_CLR0 0x0060
#define mCUR_CLR1 0x0064
#define mCUR_OFFSET 0x0068
#define mCUR_HORZ_VERT_POSN 0x006C
#define mCUR_HORZ_VERT_OFF 0x0070
#define mSCRATCH_REG0 0x0080
#define mSCRATCH_REG1 0x0084
#define mCLOCK_SEL_CNTL 0x0090
#define mBUS_CNTL 0x00A0
#define mMEM_CNTL 0x00B0
#define mMEM_VGA_WP_SEL 0x00B4
#define mMEM_VGA_RP_SEL 0x00B8
#define mDAC_REGS 0x00C0
#define mDAC_CNTL 0x00C4
#define mGEN_TEST_CNTL 0x00D0
#define mCONFIG_CHIP_ID 0x00E0
#define mCONFIG_STAT0 0x00E4
#define mCONFIG_STAT1 0x00E8
/* GUI MEMORY MAPPED Registers */
#define mDST_OFF_PITCH 0x0100
#define mDST_X 0x0104
#define mDST_Y 0x0108
#define mDST_Y_X 0x010C
#define mDST_WIDTH 0x0110
#define mDST_HEIGHT 0x0114
#define mDST_HEIGHT_WIDTH 0x0118
#define mDST_X_WIDTH 0x011C
#define mDST_BRES_LNTH 0x0120
#define mDST_BRES_ERR 0x0124
#define mDST_BRES_INC 0x0128
#define mDST_BRES_DEC 0x012C
#define mDST_CNTL 0x0130
#define mSRC_OFF_PITCH 0x0180
#define mSRC_X 0x0184
#define mSRC_Y 0x0188
#define mSRC_Y_X 0x018C
#define mSRC_WIDTH1 0x0190
#define mSRC_HEIGHT1 0x0194
#define mSRC_HEIGHT1_WIDTH1 0x0198
#define mSRC_X_START 0x019C
#define mSRC_Y_START 0x01A0
#define mSRC_Y_X_START 0x01A4
#define mSRC_WIDTH2 0x01A8
#define mSRC_HEIGHT2 0x01AC
#define mSRC_HEIGHT2_WIDTH2 0x01B0
#define mSRC_CNTL 0x01B4
#define mHOST_DATA0 0x0200
#define mHOST_DATA1 0x0204
#define mHOST_DATA2 0x0208
#define mHOST_DATA3 0x020C
#define mHOST_DATA4 0x0210
#define mHOST_DATA5 0x0214
#define mHOST_DATA6 0x0218
#define mHOST_DATA7 0x021C
#define mHOST_DATA8 0x0220
#define mHOST_DATA9 0x0224
#define mHOST_DATAA 0x0228
#define mHOST_DATAB 0x022C
#define mHOST_DATAC 0x0230
#define mHOST_DATAD 0x0234
#define mHOST_DATAE 0x0238
#define mHOST_DATAF 0x023C
#define mHOST_CNTL 0x0240
#define mPAT_REG0 0x0280
#define mPAT_REG1 0x0284
#define mPAT_CNTL 0x0288
#define mSC_LEFT 0x02A0
#define mSC_RIGHT 0x02A4
#define mSC_LEFT_RIGHT 0x02A8
#define mSC_TOP 0x02AC
#define mSC_BOTTOM 0x02B0
#define mSC_TOP_BOTTOM 0x02B4
#define mDP_BKGD_CLR 0x02C0
#define mDP_FRGD_CLR 0x02C4
#define mDP_WRITE_MASK 0x02C8
#define mDP_CHAIN_MASK 0x02CC
#define mDP_PIX_WIDTH 0x02D0
#define mDP_MIX 0x02D4
#define mDP_SRC 0x02D8
#define mCLR_CMP_CLR 0x0300
#define mCLR_CMP_MASK 0x0304
#define mCLR_CMP_CNTL 0x0308
#define mFIFO_STAT 0x0310
#define mCONTEXT_MASK 0x0320
#define mCONTEXT_LOAD_CNTL 0x0324
#define mGUI_TRAJ_CNTL 0x0330
#define mGUI_STAT 0x0338
/*
Shortened register names
*/
#define IOBASE_ADDRESS 0x02ec
#define IOB IOBASE_ADDRESS
#define CRTC_H_TOTAL ( IOB + 0x0000 )
#define CRTC_H_DISP ( IOB + 0x0002 )
#define CRTC_H_SYNC_STRT ( IOB + 0x0400 )
#define CRTC_H_SYNC_DLY ( IOB + 0x0401 )
#define CRTC_H_SYNC_WID ( IOB + 0x0402 )
#define CRTC_V_TOTAL ( IOB + 0x0800 )
#define CRTC_V_DISP ( IOB + 0x0802 )
#define CRTC_V_SYNC_STRT ( IOB + 0x0c00 )
#define CRTC_V_SYNC_WID ( IOB + 0x0c02 )
#define CRTC_OFFSET ( IOB + 0x1400 )
#define CRTC_PITCH ( IOB + 0x1402 )
#define CRTC_INT_CNTL ( IOB + 0x1800 )
#define CRTC_GEN_CNTL ( IOB + 0x1c00 )
#define CRTC_DBL_SCAN_EN 0x01
#define CRTC_INTERLACE_EN 0x02
#define CRTC_HSYNC_DIS 0x04
#define CRTC_VSYNC_DIS 0x08
#define CRTC_CSYNC_EN 0x10
#define CRTC_PIX_BY_2_EN 0x20
#define CRTC_BLANK 0x40
#define CRTC_PIX_WIDTH ( IOB + 0x1c01 )
#define PIX_WIDTH8 0x02
#define CRTC_FIFO ( IOB + 0x1c02 )
#define CRTC_EXT_DISP ( IOB + 0x1c03 )
#define CRTC_EXT_DISP_EN 0x01
#define CRTC_EXT_EN 0x02
#define OVR_CLR_8 ( IOB + 0x2000 )
#define OVR_CLR_B ( IOB + 0x2001 )
#define OVR_CLR_G ( IOB + 0x2002 )
#define OVR_CLR_R ( IOB + 0x2003 )
#define OVR_WID_LEFT ( IOB + 0x2400 )
#define OVR_WID_RIGHT ( IOB + 0x2402 )
#define OVR_WID_TOP ( IOB + 0x2800 )
#define OVR_WID_BOTTOM ( IOB + 0x2802 )
#define SCRATCH_REG0 ( IOB + 0x4000 )
#define TEST_MEM_ADDR ( IOB + 0x4000 )
#define SCRATCH_REG1 ( IOB + 0x4400 )
#define TEST_MEM_DATA ( IOB + 0x4400 )
#define CLOCK_CNTL ( IOB + 0x4800 )
#define FS2_bit 0x04
#define FS3_bit 0x08
#define CLOCK_SEL 0x0f
#define CLOCK_DIV 0x30
#define CLOCK_DIV1 0x00
#define CLOCK_DIV2 0x10
#define CLOCK_DIV4 0x20
#define CLOCK_STROBE 0x40
#define CLOCK_SERIAL_DATA 0x80
#define BUS_CNTL1_16 ( IOB + 0x4c00 )
#define BUS_CNTL2_16 ( IOB + 0x4c02 )
#define MEM_CNTL8 ( IOB + 0x5000 )
#define MEM_VGA_WP_SEL ( IOB + 0x5400 )
#define MEM_VGA_RP_SEL ( IOB + 0x5800 )
#define MEM_BNDRY ( IOB + 0x5002 )
#define MEM_BNDRY_256K 0x01
#define MEM_BNDRY_512K 0x02
#define MEM_BNDRY_1M 0x03
#define MEM_BNDRY_EN 0x04
#define DAC_W_INDEX ( IOB + 0x5c00 )
#define DAC_DATA ( IOB + 0x5c01 )
#define DAC_MASK ( IOB + 0x5c02 )
#define DAC_R_INDEX ( IOB + 0x5c03 )
#define DAC8_W_INDEX ( DAC_W_INDEX & 0xff )
#define DAC8_DATA ( DAC_DATA & 0xff )
#define DAC8_MASK ( DAC_MASK & 0xff )
#define DAC8_R_INDEX ( DAC_R_INDEX & 0xff )
#define DAC_CNTL1 ( IOB + 0x6000 )
#define DAC_EXT_SEL_RS2 0x01
#define DAC_EXT_SEL_RS3 0x02
#define DAC_CNTL2 ( IOB + 0x6001 )
#define DAC_8BIT_EN 0x01
#define DAC_PIX_DLY_MASK 0x06
#define DAC_PIX_DLY_0NS 0x00
#define DAC_PIX_DLY_2NS 0x02
#define DAC_PIX_DLY_4NS 0x04
#define DAC_BLANK_ADJ_MASK 0x18
#define DAC_BLANK_ADJ_0 0x00
#define DAC_BLANK_ADJ_1 0x08
#define DAC_BLANK_ADJ_2 0x10
#define DAC_TYPE_ ( IOB + 0x6002 )
#define GEN_TEST_CNTL ( IOB + 0x6400 )
#define CONFIG_CNTL ( IOB + 0x6800 )
#define CONFIG_CHIP_ID ( IOB + 0x6c00 )
#define CONFIG_STAT ( IOB + 0x7000 )
#define GEN_TEST_CNTL ( IOB + 0x6400 )
#define GEN_TEST_CNTL2 ( IOB + 0x6402 )
#define PIXEL_DELAY_ON 0x0800
#define PITCH_INFO (SCRATCH_REG1 + 2)
#define DAC_VGA_MODE 0x80
#define SET_VGA_MODE 0x02
#define PITCH_INFO_PSIZE 0xc0
#define PITCH_INFO_DAC 0x10
#define PITCH_INFO_MUX2 0x20
#define PITCH_INFO_TIOCLK 0x08
#define PITCH_INFO_DAC0 0x01
#define VGA_MODE 1
#define ACCELERATOR_MODE 0
#define DOTCLK_TOLERANCE 25
#define REPORT
#define DEBUG
#define BAILOUT
#define TRUE 1
#define FALSE 0
#define ATIPORT 0x1ce
#define ATIOFF 0x80
#define ATISEL(reg) (ATIOFF+reg)
#define M64_BIOS_SIZE 0x8000
#define M64_CLOCK_MAX 0x0f
#define BPP_4 1
#define BPP_8 2
#define BPP_15 3
#define BPP_16 4
#define BPP_24 5
#define BPP_32 6
#define VRAM_MASK 0x66
#define C_ISC2595 1
#define C_STG1703 2
#define C_CH8398 3
#define C_BEDROCK 4
#define C_ATT20C408 5
#define C_RGB514 6
#define D_ATI68860 5
#define SAY(x) fprintf(stderr,#x"\n");fflush(stderr);
#define DUMP(x) for (DUMPINDEX=0;DUMPINDEX<32;DUMPINDEX++) \
DUMPOUT[31-DUMPINDEX]=(((x)>>DUMPINDEX)&0x1)? \
'1':'0'; \
DUMPOUT[32]='\0'; \
printf("%s\n",DUMPOUT);
typedef unsigned char UB;
typedef unsigned short US;
typedef unsigned long UL;
typedef struct {
UB h_disp; /* horizontal res in chars */
UB dacmask; /* supported dacs */
UB ram_req; /* ram required */
UB max_dot_clk; /* max dot clock */
UB color_depth; /* mac color depth */
UB FILLER; /* make even #bytes */
} M64_MaxColorDepth;
typedef struct {
UB ClockType; /* clock type */
US MinFreq; /* min clock freq */
US MaxFreq; /* max clock freq */
US RefFreq; /* reference freq */
US RefDivdr; /* reference freq divider */
US N_adj; /* adjust */
US Dram_Mem_Clk;
US Vram_Mem_Clk;
US Coproc_Mem_Clk;
UB CX_Clk;
UB VGA_Clk;
UB Mem_Clk_Entry;
UB SClk_Entry;
US ClkFreqTable[M64_CLOCK_MAX*2]; /* clock frequency table */
UB DefaultDivdr;
UB DefaultFS2;
UB CX_DMcycle;
UB VGA_DMcycle;
UB CX_VMcycle;
UB VGA_VMcycle;
} M64_ClockInfo;
typedef struct {
US Chip_Type; /* ASIC Chip type */
UB Chip_Class; /* ASIC Chip class */
UB Chip_Rev; /* ASIC Chip Revision */
UB Chip_ID_Index; /* Name offset */
UB Cfg_Bus_type; /* Bus type */
UB Cfg_Ram_type; /* Ram type */
UB Mem_Size; /* Memory installed */
UB Dac_Type; /* Dac type */
UB Dac_Subtype; /* Dac sub type */
} M64_StartUpInfo;
static UB *M64_Chip_Name[]={"GX-C","GX-D","GX-E","GX-F","GX-?",
"CX","CX-?",
"CT","ET",
"?"};
static UB *M64_Bus_Name[]={"ISA","EISA","","","","","VLB","PCI"};
static UB *M64_Dac_Name[]={"","TVP3020, RGB514","ATI68875","BT476/BT478",
"BT481, ATT490, ATT491","ATI68860/ATI68880",
"STG1700","SC15021, STF1702"};
static UB *M64_Ram_Name[]={"DRAM (256Kx4)","VRAM (256x4,x8,x16)",
"VRAM (256Kx16 short shift register)",
"DRAM (256Kx16)","Graphics DRAM (256Kx16)",
"Enhanced VRAM (256Kx4,x8,x16)",
"Enhanced VRAM (256Kx16 short shift register)",
""};
static US M64_Mem_Size[]={512,1024,2048,4096,6144,8192,0,0};
static UB *M64_Clock_Name[]={"","ISC2595","STG1703","CH8398",
"BEDROCK","ATT20C408","RGB514"};
static UB M64_BPP[]={-1,4,8,15,16,24,32,-1};
/*
Some misc. structures
*/
typedef struct {
US VRes;
US HRes;
UB max_cdepth;
UB req_cdepth;
US fifo_vl;
US pdot_clock;
UB refresh_mask;
UB vmode;
US misc;
UB h_total;
UB h_disp;
UB h_sync_strt;
UB h_sync_wid;
US v_total;
US v_disp;
US v_sync_strt;
UB v_sync_wid;
UB clock_cntl;
US dot_clock;
UB h_overscan_a;
UB h_overscan_b;
UB v_overscan_a;
UB v_overscan_b;
UB overscan_8;
UB overscan_B;
UB overscan_G;
UB overscan_R;
} CRTC_Table;
#define MAX_CRTC_TABLE 1
static CRTC_Table CRTC_tinfo[MAX_CRTC_TABLE]={
/* 640x480 60 Hz NI */
{ 0, 0, 0, 0, 0,
0, 60, 0x12, PIXEL_DELAY_ON,
/* 0x63, 0x4f, 0x52, 0x2c,
0x020c, 0x01df, 0x01ea, 0x22,
*/ 0x64, 0x50, 0x53, 0x02,
0x20d, 0x1e0, 0x1eb, 0x02,
0x00, 2518,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
}
};

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This contains the source for a Borland C++ program that allows you to dump
the register contents for any BIOS video mode. 'vga.exe' should work with
any VGA/SVGA adapter. It takes a hexadecimal mode number as argument and
writes the (VGA) register contents to the console.
These printout can be used to write a new driver. Please read also 'man 7
svgalib.et4000' about the tseng3.exe program.
trap-out.asm / .com is a DOS program which traces all I/O calls made when a
given video mode is set by the BIOS. It was used for the TVGA driver and should
be useful for other drivers too, esp. if no documentation is available.
It spits out a long list of "T DX/I AX/L" strings where T is "I" for IN or
"O" for OUT, DX/I is the value of DX or the immediate given value for
ports <256, and AX/L is the value of AX or AL before the call to IN or OUT
(yeah, the value of AX is pretty worthless before a call to IN, but oh
well)
This output is very very easily parsed into a simple C routine that calls
port_in and port_out many many times, but will set the same mode the BIOS
did.
The trap-out program is courtesy of Ryan Rubley <rubleyr@river.it.gvsu.edu>

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; TRAPOUT2.ASM v2.0 by ARK (ark@lhq.com, root@ark.dyn.ml.org) 11-28-97
; Traps IN and OUT instructions in INT 10h and displays DX and AX/AL values.
;
; In the header "T DX/I AX/L", T is the Type of instruction (I=IN, O=OUT),
; DX/I is the value of DX or the Immediate value if port<256, and AX/L
; is the value of AX or AL depending on if an 8 or 16 bit value is listed.
; AX/L is meaningless for IN's since it is the value if AX/L *before* the
; call to IN.
;
; This is very useful to find information about how your video card works.
; I wrote this to get register dumps for my Trident TVGA9440AGi card so
; that I could use it under Linux.
;
; NOTE: Pipe the output or you won't see anything!
; (ex: TRAP-OUT 4F02 0101 > 640x480.256)
;
; New in v2.0:
; * Traces into INT 10 calls that are called from inside INT 10!
; * Allows AX and BX values to be specified!
; * Command line accepts trailing spaces now.
; x Code to trap INT's also! (T column='N', DX/I=INT ##, AX/L=AX value)
; (Its commented out - but you can recompile with it if you want)
;
; How to assemble with Borland:
; tasm /ml /zd ncr.asm (case sensitive, line number debug info only)
; tlink /x /t ncr.obj (no map, make com file)
;
.model tiny ; Tiny memory model, all segments point to the same 64K
.286 ; This code will run on a 286... actually, it
.code ; Everything is in the code segment(cs) will probably
.startup ; Startup run on anything
jmp Start ; Go to beginning of progam
realINT1 dd 52411A3Eh ; Address of original INT 01h routine offset
realINT10 dd 3C1B214Bh ; Memory for [es:bx] of the real INT 10h
; (defaults are '>-ARK!-<' just for looks in the .COM)
; strings
no_command_line db 'Use: TRAPOUT2 [AX] [BX]',13,10
db ' Traces all IN/OUT calls inside INT 10h',13,10,36
tracing db 'Tracing INT 10h with AX:',36
bx_msg db ' BX:',36
header db 13,10,'T DX/I AX/L',13,10,36
INT1 proc ; Interrupt Service Routine for Single Step Debugging
push ax ; save registers
push dx
push es
push di
push bp
mov bp,sp ; set bp to the stack
push word ptr cs:[bp+12] ; put the real cs
pop es ; into es
push word ptr cs:[bp+10] ; put the real ip
pop di ; into di
mov al,byte ptr es:[di] ; set al to the next instruction that will
; be executed after this INT 01 is done.
; This code will trap INT's also...
; cmp al,0CDh ; If al is not CD (INT) keep going
; jne not_int ; If it is, display some stuff...
;; This will skip doing the INT's...
;; add word ptr cs:[bp+10],2 ; Add 2 to the real ip, to skip the INT
; mov dl,4Eh ; Display an N
; mov ah,02h ; The immediate value/DX is the INT ##
; int 21h ; that is called. AX is the value before
; mov dl,20h ; Display a space
; mov ah,02h ;
; int 21h ; Display the immediate value which is
; jmp is_imm ; reallly the interrupt number called.
not_int:
and al,0F4h ; If al is E4-E7 or EC-EF (all IN/OUT's)
cmp al,0E4h ; Then we display our stuff
jne not_io ; Otherwise, do nothing
; note: 1 more byte of code after this
; jmp will make it out of range...
mov al,byte ptr es:[di] ; Set al to next instruction
test al,02h ; If bit 1 is set then we have an OUT
jz is_in ; If bit 1 is 0, we have an IN
mov dl,4Fh ; Display an O
mov ah,02h
int 21h
jmp dx_or_imd
is_in: ; Display an I
mov dl,49h
mov ah,02h
int 21h
dx_or_imd: ; Display a space
mov dl,20h
mov ah,02h
int 21h
mov al,byte ptr es:[di] ; Set al to next instruction
test al,08h ; If bit 3 is set then we are using DX
jz is_imm ; If bit 3 is 0, we are using an immediate
mov ax,[bp+6] ; restore dx to ax
call ShowHex ; Display dx
call ShowHex
call ShowHex
call ShowHex
jmp ax_or_al
is_imm:
mov dl,20h ; Display 2 spaces
mov ah,02h
int 21h
mov dl,20h
mov ah,02h
int 21h
mov ah,byte ptr es:[di+1] ; Set ah to byte after the next instruction
call ShowHex ; Display the immediate value
call ShowHex
ax_or_al:
mov dl,2Ch ; Display a comma
mov ah,02h
int 21h
mov al,byte ptr es:[di] ; Set al to next instruction
test al,01h ; If bit 0 is set then we are using AX
jz is_al ; If bit 0 is 0, we are using AL
mov ax,[bp+8] ; Restore ax
call ShowHex ; Display ax
call ShowHex
call ShowHex
call ShowHex
jmp print_next_line
is_al:
mov ah,[bp+8] ; Restore al to ah
call ShowHex ; Display al
call ShowHex
print_next_line:
mov dl,0Dh ; print a newline
mov ah,02h
int 21h
mov dl,0Ah
mov ah,02h
int 21h
not_io:
pop bp ; restore registers
pop di
pop es
pop dx
pop ax
iret ; end interrupt
INT1 endp
; INT 10h that fakes the real INT 10 and sets the trap flag.
INT10 proc ; Interrupt Service Routine for Tracing INT 10h
push ax ; Save AX
pushf ; Put flags on the stack
pop ax ; Then into AX
or ax,0100h ; Set the trap flag
push ax ; Trap Flag calls INT 01h between every instruction
popf ; Stuff new flags back into the flags register
pop ax ; Restore AX
cli ; Fake INT call: clear interrupt flag, skip clearing
pushf ; trap flag, push flags, call to location.
call cs:[realINT10] ; This call to INT 10h is be trapped for
; IN/OUT/INT Normal INT calls would clear
; the trap flag and then INT 01h would never
; be called.
iret ; end interrupt
INT10 endp
; function that prints the highest 4 bits of ax as text {0-9,A-F} to stdout
; ax will be shifted left 4 bits on return.
ShowHex proc
push ax ; save registers
push dx
shr ax,0Ch ; move the highest 4 bits to the lowest 4
and al,0Fh ; limit to lowest 4 bits
or al,30h ; change range to 30h-3Fh {0-9:;<=>?}
cmp al,39h ; if it is 30h-39h
jbe is_0_thru_9 ; then its already set
add al,07h ; otherwise change :;<=>? to A-F
is_0_thru_9:
mov dl,al
mov ah,02h
int 21h
pop dx ; restore dx
pop ax ; restore ax
shl ax,4 ; set up ax for next call
ret ; return
ShowHex endp
Start: ; Program begins here
mov si,0080h ; CS:0080h is the command line
cmp byte ptr [si],10 ; I want it to be at least 10 bytes long
jae process_command_line ; if not, abort
mov dx,offset no_command_line ; ds is preset
mov ah,09h ; Dos function 09h
int 21h ; Display no command line string
ret ; Exit program
process_command_line:
inc si ; move si to start of actual string
mov ax,[si+1] ; copy first 2 chrs to ax, skipping the space
mov bx,[si+3] ; copy 2nd two characters to bx
sub al,30h ; subtract 30h so chrs 0-9 have value 0-9
cmp al,09h ; if its 0-9, its ok.
jbe al_is_ok ; if its not, its probably A-F or a-f
sub al,07h ; so subtract 7 more
and al,0Fh ; and limit to 0-F
al_is_ok:
sub ah,30h ; do the same to ah
cmp ah,09h
jbe ah_is_ok
sub ah,07h
and ah,0Fh
ah_is_ok:
sub bl,30h ; do the same to bl
cmp bl,09h
jbe bl_is_ok
sub bl,07h
and bl,0Fh
bl_is_ok:
sub bh,30h ; do the same to bh
cmp bh,09h
jbe bh_is_ok
sub bh,07h
and bh,0Fh
bh_is_ok:
shl al,04h ; Combine the values so that AL-AH-BL-BH
or ah,al ; Goes into --AH- --AL-
mov al,bl ; <----AX--->
shl al,04h
or al,bh
mov word ptr [si],ax ; store the value over the string
mov ax,[si+6] ; copy 3rd 2 chrs to ax, skip the 2nd space
mov bx,[si+8] ; copy 4th two characters to bx
sub al,30h ; subtract 30h so chrs 0-9 have value 0-9
cmp al,09h ; if its 0-9, its ok.
jbe al_is_ok2 ; if its not, its probably A-F or a-f
sub al,07h ; so subtract 7 more
and al,0Fh ; and limit to 0-F
al_is_ok2:
sub ah,30h ; do the same to ah
cmp ah,09h
jbe ah_is_ok2
sub ah,07h
and ah,0Fh
ah_is_ok2:
sub bl,30h ; do the same to bl
cmp bl,09h
jbe bl_is_ok2
sub bl,07h
and bl,0Fh
bl_is_ok2:
sub bh,30h ; do the same to bh
cmp bh,09h
jbe bh_is_ok2
sub bh,07h
and bh,0Fh
bh_is_ok2:
shl al,04h ; Combine the values so that AL-AH-BL-BH
or ah,al ; Goes into --AH- --AL-
mov al,bl ; <----AX--->
shl al,04h
or al,bh
mov word ptr [si+2],ax ; store the value over the string
; Now [si] contains the real values of AX and BX
mov dx,offset tracing ; ds is preset
mov ah,09h ; Dos function 09h
int 21h ; Display tracing string
mov ax,word ptr [si] ; Restore ax
call ShowHex ; Display command line
call ShowHex ; ax value back to user
call ShowHex ; by placing it in ax
call ShowHex ; and calling ShowHex
mov dx,offset bx_msg ; ds is preset
mov ah,09h ; Dos function 09h
int 21h ; Display bx message
mov ax,word ptr [si+2] ; Restore bx into ax
call ShowHex ; Display command line
call ShowHex ; bx value back to user
call ShowHex ; by placing it in ax
call ShowHex ; and calling ShowHex
mov dx,offset header ; ds is preset
mov ah,09h ; Dos function 09h
int 21h ; Display header to output
mov ax,3501h ; Dos function 35h, Get vector of INT 01h
int 21h ; Store it in es:bx
mov word ptr [realINT1],bx ; Store address of original INT 01h
mov word ptr [realINT1+2],es ; into realINT1
mov ax,3510h ; Dos function 35h, Get vector of INT 10h
int 21h ; Store it in es:bx
mov word ptr [realINT10],bx ; Store address of original INT 10h
mov word ptr [realINT10+2],es ; into realINT10 so we can fake an INT
mov ax,2501h ; Dos function 25h, Store DS:DX to INT 01h
mov dx,offset INT1 ; ds is preset, dx is the handler's offset
int 21h ; Set new Single Step handler
mov ax,2510h ; Dos function 25h, Store DS:DX to INT 10h
mov dx,offset INT10 ; ds is preset, dx is the handler's offset
int 21h ; Set new Video Interrupt
mov ax,word ptr [si] ; We will use the command line ax/bx
mov bx,word ptr [si+2] ; values for the fake int call
int 10h ; Call my int 10 which fakes the
; real int 10 and traps it.
mov ax,2501h ; Dos function 25h, Store DS:DX to INT 01h
mov dx,word ptr [realINT1] ; ds/dx are in realINT1
push ds ; Save old ds
push word ptr [realINT1+2] ; Put segment on stack
pop ds ; Set ds to the segment
int 21h ; Reset old Single Step handler
pop ds ; Restore old ds
mov ax,2510h ; Dos function 25h, Store DS:DX to INT 10h
mov dx,word ptr [realINT10] ; ds/dx are in realINT10
push ds ; Save old ds
push word ptr [realINT10+2] ; Put segment on stack
pop ds ; Set ds to the segment
int 21h ; Reset old Video Interrupt
pop ds ; Restore old ds
mov ax,0003h ; Set ax to 3
int 10h ; Set 80x25 Text mode
ret ; End of program
end ; End of file

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#include <stdio.h>
#include <stdlib.h>
#include <dos.h>
/* January 1995, Scott Heavner (sdh@po.cwru.edu)
* Changes to allow anyone to compile vga.c under the go32 Linux->dos cross compiler.
* It should also work with DJGPP (the gcc port to msdos). The cross compiler is
* available at ftp://sunsite.unc.edu/pub/Linux/devel/msdos/go32crs.tar.gz.
*
* I compiled it with:
*
* go32gcc vga.c -lpc
* cat /usr/local/go32/bin/go32.exe a.out > vga.exe
*/
#ifdef GO32
#include <pc.h>
#endif
/* VGA index register ports */
#define CRT_I 0x3D4 /* CRT Controller Index (mono: 0x3B4) */
#define ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
#define GRA_I 0x3CE /* Graphics Controller Index */
#define SEQ_I 0x3C4 /* Sequencer Index */
#define PEL_IW 0x3C8 /* PEL Write Index */
/* VGA data register ports */
#define CRT_D 0x3D5 /* CRT Controller Data Register (mono: 0x3B5) */
#define ATT_R 0x3C1 /* Attribute Controller Data Read Register */
#define GRA_D 0x3CF /* Graphics Controller Data Register */
#define SEQ_D 0x3C5 /* Sequencer Data Register */
#define MIS_R 0x3CC /* Misc Output Read Register */
#define MIS_W 0x3C2 /* Misc Output Write Register */
#define IS1_R 0x3DA /* Input Status Register 1 (mono: 0x3BA) */
#define PEL_D 0x3C9 /* PEL Data Register */
/* VGA indexes max counts */
#define CRT_C 24 /* 24 CRT Controller Registers */
#define ATT_C 21 /* 21 Attribute Controller Registers */
#define GRA_C 9 /* 9 Graphics Controller Registers */
#define SEQ_C 5 /* 5 Sequencer Registers */
#define MIS_C 1 /* 1 Misc Output Register */
/* VGA registers saving indexes */
#define CRT 0 /* CRT Controller Registers start */
#define ATT CRT+CRT_C /* Attribute Controller Registers start */
#define GRA ATT+ATT_C /* Graphics Controller Registers start */
#define SEQ GRA+GRA_C /* Sequencer Registers */
#define MIS SEQ+SEQ_C /* General Registers */
#define END MIS+MIS_C /* last */
unsigned char vga_regs[60];
#ifdef GO32
#define port_out(v,p) outportb(p,v)
#define port_in(p) inportb(p)
#else
void port_out(unsigned char value, unsigned short port)
{
asm
{
mov dx, port
mov al, value
out dx, al
}
} unsigned char port_in(unsigned short port)
{
asm
{
mov dx, port
in al, dx
} return (_AL);
}
#endif
main(int argc, char *argv[])
{
union REGS cpu_regs;
int i;
unsigned char mode;
if (argc != 2) {
printf("Usage: getregs mode (mode must be hexadecimal)\n");
exit(-1);
}
if (!sscanf(argv[1], "%x", &mode)) {
printf("Usage: getregs mode (mode must be hexadecimal)\n");
exit(-1);
}
cpu_regs.h.ah = 0x00;
cpu_regs.h.al = mode;
int86(0x10, &cpu_regs, &cpu_regs);
/* get VGA register values */
for (i = 0; i < CRT_C; i++) {
port_out(i, CRT_I);
vga_regs[CRT + i] = port_in(CRT_D);
}
for (i = 0; i < ATT_C; i++) {
port_in(IS1_R);
port_out(i, ATT_IW);
vga_regs[ATT + i] = port_in(ATT_R);
}
for (i = 0; i < GRA_C; i++) {
port_out(i, GRA_I);
vga_regs[GRA + i] = port_in(GRA_D);
}
for (i = 0; i < SEQ_C; i++) {
port_out(i, SEQ_I);
vga_regs[SEQ + i] = port_in(SEQ_D);
}
vga_regs[MIS] = port_in(MIS_R);
cpu_regs.h.ah = 0x00;
cpu_regs.h.al = 0x03;
int86(0x10, &cpu_regs, &cpu_regs);
printf("/* BIOS mode 0x%02X */\n", mode);
printf("static char regs[60] = {\n ");
for (i = 0; i < 12; i++)
printf("0x%02X,", vga_regs[CRT + i]);
printf("\n ");
for (i = 12; i < CRT_C; i++)
printf("0x%02X,", vga_regs[CRT + i]);
printf("\n ");
for (i = 0; i < 12; i++)
printf("0x%02X,", vga_regs[ATT + i]);
printf("\n ");
for (i = 12; i < ATT_C; i++)
printf("0x%02X,", vga_regs[ATT + i]);
printf("\n ");
for (i = 0; i < GRA_C; i++)
printf("0x%02X,", vga_regs[GRA + i]);
printf("\n ");
for (i = 0; i < SEQ_C; i++)
printf("0x%02X,", vga_regs[SEQ + i]);
printf("\n ");
printf("0x%02X", vga_regs[MIS]);
printf("\n};\n");
}

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/*
* This is a quickly hacked program to convert an SVPMI (Super VGA Protected
* Mode Interface) data file to an svgalib driver. Feedback is
* very welcome.
*
* Initial version (Mar 94 HH). Doesn't do much yet.
* Assumes textmode is last defined mode.
* End with ctrl-c. Correct resulting files by hand.
* (add "}" to modetable.svpmi)
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
void parse ();
void
main ()
{
parse ();
}
/* Return pointer to line red from stdin, end marked by CR or CR/LF.
* Initial spaces are removed. */
char *
getline ()
{
static char linebuf[128];
int i, length, spaces;
i = 0;
for (;;)
{
int c;
c = fgetc (stdin);
if (feof (stdin))
return NULL;
if (c == 13)
continue; /* Skip. */
if (c == 10)
break;
linebuf[i] = c;
i++;
}
length = i;
linebuf[i] = 0;
/* Remove initial spaces. */
spaces = 0;
i = 0;
while (i < length)
{
if (linebuf[i] != ' ')
break;
i++;
spaces++;
}
return linebuf + spaces;
}
/* Skip lines until left side of line matches string s. */
char *
getthisline (char *s)
{
char buf[128];
int n;
n = strlen (s);
for (;;)
{
char *line;
line = getline ();
if (strncmp (line, s, n) == 0)
return line;
}
}
/* Get the (n + 1)th word delimited by ' ' and ';' in string s. */
char *
getword (char *s, int n)
{
int i;
char *word;
int mode, wcount;
word = s;
mode = 0; /* Whitespace. */
wcount = 0;
i = 0;
for (i = 0; s[i] != 0; i++)
{
if (s[i] == ' ' || s[i] == ';')
if (mode == 0)
continue;
else
{
s[i] = 0;
if (wcount == n)
return word;
wcount++;
mode = 0;
}
else if (mode == 1)
continue;
else
{
word = &s[i];
mode = 1;
}
}
return NULL;
}
/* Write lines to file until left part matches string s. */
void
writetofileuntilthisline (char *s, FILE * f)
{
int n;
n = strlen (s);
for (;;)
{
char *line;
line = getline ();
if (strncmp (line, s, n) == 0)
break;
fprintf (f, "%s\n", line);
}
}
void
writetofileuntilend (FILE * f)
{
for (;;)
{
char *line;
line = getline ();
if (line == NULL)
return;
fprintf (f, "%s\n", line);
}
}
void
parse ()
{
char *line;
char s[128];
char modename[40];
int modenumber;
FILE *f, *g;
printf ("SVPMI to svgalib driver converter.\n\n");
/* Read header. */
getthisline ("[ADAPTER]");
line = getline ();
printf ("Graphics Adapter string: %s\n", line);
/* Read modes. */
modenumber = 0;
g = fopen ("modetable.svpmi", "wb");
f = fopen ("modes.svpmi", "wb");
fprintf (g, "/* svgalib SVPMI mode table. */\n\n");
fprintf (g, "static svpmi_modeentry svpmi_modes[] = {\n");
for (;;)
{
int XResolution; /* SVPMI modeinfo fields. */
int YResolution;
int BitsPerPixel;
int BytesPerScanline;
int WinAGranularity;
int WinASize;
int WinABase;
int ModeAttributes;
getthisline ("[MODEINFO]");
line = getthisline ("ModeAttributes");
ModeAttributes = atoi (getword (line, 2));
line = getthisline ("WinAGranularity");
WinAGranularity = atoi (getword (line, 2));
line = getthisline ("WinASize");
WinASize = atoi (getword (line, 2));
line = getthisline ("WinABase");
WinABase = atoi (getword (line, 2));
#if 0
if (WinABase != 0xa0000)
{
printf ("Window is not at 0xa0000.\n");
exit (-1);
}
#endif
line = getthisline ("BytesPerScanline");
BytesPerScanline = atoi (getword (line, 2));
line = getthisline ("XResolution");
XResolution = atoi (getword (line, 2));
line = getthisline ("YResolution");
YResolution = atoi (getword (line, 2));
line = getthisline ("BitsPerPixel");
BitsPerPixel = atoi (getword (line, 2));
if (ModeAttributes == 0x07)
{
/* Text mode. */
printf ("Textmode found.\n");
getthisline ("[SETMODE]");
fprintf (f, "static void svpmi_setmode_text() {\n");
writetofileuntilend (f);
fprintf (f, "}\n\n\n");
fprintf (g, "}\n");
fclose (f);
fclose (g);
exit (0);
}
printf ("Mode found: %d x %d, %dbpp %d bpl gran A %d\n",
XResolution, YResolution, BitsPerPixel,
BytesPerScanline, WinAGranularity);
sprintf (modename, "%dx%dx%d", XResolution, YResolution,
1 << BitsPerPixel);
getthisline ("[SETMODE]");
fprintf (f, "static void svpmi_setmode_%s() {\n", modename);
writetofileuntilthisline ("[SETCOLOR]", f);
fprintf (f, "}\n\n\n");
getthisline ("[SETWINDOW]");
fprintf (f, "static void svpmi_setwindow_%s( int r0 ) {\n", modename);
writetofileuntilthisline ("[MODE]", f);
fprintf (f, "}\n\n\n");
fprintf (g, "{ %d, %d, %d, %d, %d, svpmi_setmode_%s, svpmi_setwindow_%s },\n",
XResolution, YResolution, BitsPerPixel,
BytesPerScanline, WinAGranularity, modename, modename);
fflush (f);
fflush (g);
modenumber++;
}
fprintf (g, "}\n");
fclose (f);
fclose (g);
}

185
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/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
/* Copyright (C) 1994 Harm Hanemaayer */
/*
Basic initial untested SVPMI skeleton driver.
Includes computer-generated mode setting/bank switching
routines and mode information table.
Untested, may not be finished.
A better way to do this would be to have a seperate svpmi server
program set modes. This way there would be no need to recompile
the shared library. For performance it would be nice to move the
bank-switching over to svgalib. I imagine one way to do this would
be to encode the SVPMI procedure code (simple as it is, just a few
outs and a few basic bit operations) and have the svgalib driver
interpret that. This could also be used for mode setting.
*/
#include <stdio.h>
#include "../vga.h"
#include "../libvga.h"
#include "../driver.h"
#include "svpmi.h"
#include "modes.svpmi"
#include "modetable.svpmi"
static svpmi_currentmode = NULL;
static svpmi_modeentry *
svpmi_lookupmode (int w, int h, int colors)
{
int i;
for (i = 0; i < sizeof (svpmi_modes); i++)
if (w == svpmi_modes[i].width && h == svpmi_modes[i].height &&
colors = (1 << svpmi_mode[i].bitsperpixel))
return &svpmi_modes[i];
return NULL;
}
static int
svpmi_getmodeinfo (int mode, vga_modeinfo * modeinfo)
{
modeinfo->maxlogicalwidth = modeinfo->width;
modeinfo->startaddressrange = 0;
modeinfo->haveblit = 0;
modeinfo->flags &= ~HAVE_RWPAGE;
return 0;
}
/* Return non-zero if mode is available */
static int
svpmi_modeavailable (int mode)
{
struct info *info;
svpmi_modeentry *sm;
if (mode < 10)
return vga_chipsetfunctions[CHIPSET_MODEAVAILABLE] (mode);
if (mode == 32)
return 0;
sm = svpmi_lookupmode (modeinfo->width, modeinfo->height,
modeinfo->colors);
return (sm != NULL)
}
/* Set a mode */
static int
svpmi_setmode (int mode, int prv_mode)
{
svpmi_modeentry *sm;
if (mode == TEXT)
{
svpmi_setmode_text ();
return 0;
}
if (!SVGAMODE (mode))
/* Let the standard VGA driver set standard VGA modes. */
return vga_chipsetfunctions[CHIPSET_SETMODE] (mode);
sm = svpmi_lookupmode (infotable[mode].width, infotable[mode].height,
infotable[mode].colors);
if (sm == NULL)
return 1; /* No match. */
sm->setmode (); /* Call the SVPMI mode setting code. */
svpmi_currentmode = sm;
/* Hack similar to what the ATI mach32 driver does for some */
/* truecolor modes. I think S3 uses only a few fixed scanline */
/* widths (e.g. 1024, 1280) so may happen a lot. */
infotable[mode].xbytes = sm->bytesperscanline;
}
/* Indentify chipset; return non-zero if detected */
static int
svpmi_test ()
{
/* Detection with environment variable -- better change into */
/* config file option. */
if (getenv ("SVGALIB_SVPMI"))
return 1;
return 0;
}
/* Bank switching function - set 64K bank number */
static void
svpmi_setpage (int page)
{
svpmi_currentmode->setwindow (page *
(64 / svpmi_currentmode->windowgranularity));
}
/* Set display start address (not for 16 color modes) */
static int
svpmi_setdisplaystart (int address)
{
}
/* Set logical scanline length (usually multiple of 8) */
/* Multiples of 8 to 2040 */
static int
svpmi_setlogicalwidth (int width)
{
outw (0x3d4, 0x13 + (width >> 3) * 256); /* lw3-lw11 */
return 0;
}
static int
nothing ()
{
}
/* Function table (exported) */
int (*svpmi_chipsetfunctions[]) () =
{
(int (*)()) nothing, /* saveregs */
(int (*)()) nothing, /* setregs */
(int (*)()) nothing, /* unlock */
(int (*)()) nothing, /* lock */
svpmi_test,
svpmi_init,
(int (*)()) svpmi_setpage,
(int (*)()) nothing,
(int (*)()) nothing,
svpmi_setmode,
svpmi_modeavailable,
nothing, /* setdisplaystart */
svmi_setlogicalwidth,
svpmi_getmodeinfo
};
/* Initialize chipset (called after detection) */
static int
svpmi_init (int force, int par1, int par2)
{
/* Not required. */
}

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typdef struct
{
int width;
int height;
int bitsperpixel;
int bytesperscanline;
int windowgranularity;
void *setmode ();
void *setwindow (int);
}
svpmi_modeentry;
static void
wait (int x)
{
int i;
for (i = 0; i < 10; i++);
}
static unsigned char r0, r1, r2, r3, r4, r5, r6, r7;
static unsigned char r8, r9, r10, r11, r12, r13, r14, r15;
static unsigned char r16, r17, r18, r19, r20, r21, r22, r23;
static unsigned char r24, r25, r26, r27, r28, r29, r30, r31;
#define boutb(n, p1, p2) __boutb(0, n, p1 p2)
#define __boutp(i, n, p1, p2) \
#if n != 0 \
outb(p1, i); outb(p2, r##i); \
boutb((i + 1), (n - 1), p1, p2); \
#endif
#define inb(r, p) port_in(p)
#define and(r, v) r &= v;
#define or(r, v) r |= v;
#define xor(r, v) r ^= v;
#define shr(r, v) r >>= v;
#define shl(r, v) r <<= v;